Discussion:
[PATCH 00/11] Port the FSL QSPI driver to the SPI framework
(too old to reply)
Frieder Schrempf
2018-05-30 13:14:29 UTC
Permalink
Now that the SPI memory interface was introduced by Boris [1], it is
possible to move drivers from mtd/spi-nor to the SPI framework in order
to use them for different type of SPI memory chips.

Patch 1 adds a function spi_mem_get_name() to the SPI memory interface,
and patch 2 uses it in m25p80.c to make it possible for SPI controller
drivers to provide a custom naming scheme for the flash chip.
This is needed to avoid breaking compatibility of mtdparts when switching
from the old to the new driver.

Patch 3 adds a driver for the Freescale QSPI controller to the SPI
framework. Together with m25p80.c it can be used to interface SPI
NOR flashes just as the old driver did. For this to work properly a few
minor changes to the devicetrees are necessary (see patches 4,5 and 6).

Patch 7 changes the defconfigs to use the new driver and patch 8 removes
the old driver.

Patch 9 and 10 remove 'fsl,qspi-has-second-chip' from the devicetrees.
Patch 11 adjusts the MAINTAINERS file.

The new driver was tested with i.MX6UL and a Micron SPI NOR @ 60MHz.
The read performance of the new driver is almost the same or even better
than the old driver, depending on the block size.
The write performance is a bit slower on average (~10-15%).

The new driver was also tested with the SPI NAND framework [2] and a
Winbond W25M02GV flash.

If someone has a board that uses both chips selects and/or both busses,
it would be really nice to have the driver be tested on such a setup.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/commit/?h=for-4.18&id=c36ff266dc82f4ae797a6f3513c6ffa344f7f1c7
[2] https://patchwork.ozlabs.org/cover/913728/

Frieder Schrempf (11):
spi: spi-mem: Extend the SPI mem interface to set a custom memory name
mtd: m25p80: Call spi_mem_get_name() to let controller set a custom
name
spi: Add a driver for the Freescale/NXP QuadSPI controller
dt-bindings: spi: Move and adjust the bindings for the fsl-qspi driver
ARM: dts: Reflect change of FSL QSPI driver and remove unused
properties
arm64: dts: Reflect change of FSL QSPI driver and remove unused
properties
ARM: defconfig: Use the new FSL QSPI driver under the SPI framework
mtd: fsl-quadspi: Remove the driver as it was replaced by
spi-fsl-qspi.c
ARM: dts: ls1021a: Remove fsl,qspi-has-second-chip as it is not used
ARM64: dts: ls1046a: Remove fsl,qspi-has-second-chip as it is not used
MAINTAINERS: Move the Freescale QSPI driver to the SPI framework

.../devicetree/bindings/mtd/fsl-quadspi.txt | 65 -
.../devicetree/bindings/spi/spi-fsl-qspi.txt | 69 +
MAINTAINERS | 4 +-
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 8 +-
arch/arm/boot/dts/imx6sx-sdb.dts | 8 +-
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 +
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 6 +-
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
.../boot/dts/freescale/fsl-ls1043a-qds.dts | 3 +-
.../boot/dts/freescale/fsl-ls1046a-qds.dts | 4 +-
.../boot/dts/freescale/fsl-ls1046a-rdb.dts | 6 +-
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
.../boot/dts/freescale/fsl-ls208xa-qds.dtsi | 4 +
drivers/mtd/devices/m25p80.c | 3 +-
drivers/mtd/spi-nor/Kconfig | 9 -
drivers/mtd/spi-nor/Makefile | 1 -
drivers/mtd/spi-nor/fsl-quadspi.c | 1206 ------------------
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-fsl-qspi.c | 929 ++++++++++++++
drivers/spi/spi-mem.c | 25 +
include/linux/spi/spi-mem.h | 3 +
23 files changed, 1071 insertions(+), 1301 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
delete mode 100644 drivers/mtd/spi-nor/fsl-quadspi.c
create mode 100644 drivers/spi/spi-fsl-qspi.c
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:30 UTC
Permalink
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility with the old drivers naming scheme, a function
is added to the SPI mem interface to let controller drivers set a
custom name for the memory.

Example for the FSL QSPI driver:

Name with the old driver: 21e0000.qspi,
or with multiple devices: 21e0000.qspi-0, 21e0000.qspi-1, ...

Name with the new driver without spi_mem_get_name: spi4.0

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
drivers/spi/spi-mem.c | 25 +++++++++++++++++++++++++
include/linux/spi/spi-mem.h | 3 +++
2 files changed, 28 insertions(+)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 990770d..5e9af47 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -311,6 +311,31 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
EXPORT_SYMBOL_GPL(spi_mem_exec_op);

/**
+ * spi_mem_get_name() - Let drivers using the SPI mem interface specify a
+ * custom name for the memory to avoid compatibility
+ * issues with ported drivers.
+ * @mem: the SPI memory
+ *
+ * When porting (Q)SPI controller drivers from the MTD layer to the SPI
+ * layer, the naming scheme for the memory devices changes. To be able to
+ * keep compatibility with the old drivers naming scheme, this function can
+ * be used to get a custom name from the controller driver.
+ * If no custom name is available, the name of the SPI device is returned.
+ *
+ * Return: a char array that contains the name for the flash memory
+ */
+const char *spi_mem_get_name(struct spi_mem *mem)
+{
+ struct spi_controller *ctlr = mem->spi->controller;
+
+ if (ctlr->mem_ops && ctlr->mem_ops->get_name)
+ return ctlr->mem_ops->get_name(mem);
+
+ return dev_name(&mem->spi->dev);
+}
+EXPORT_SYMBOL_GPL(spi_mem_get_name);
+
+/**
* spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
* match controller limitations
* @mem: the SPI memory
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 4fa34a2..f1912d3 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -178,6 +178,7 @@ struct spi_controller_mem_ops {
const struct spi_mem_op *op);
int (*exec_op)(struct spi_mem *mem,
const struct spi_mem_op *op);
+ const char *(*get_name)(struct spi_mem *mem);
};

/**
@@ -236,6 +237,8 @@ bool spi_mem_supports_op(struct spi_mem *mem,
int spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op);

+const char *spi_mem_get_name(struct spi_mem *mem);
+
int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
struct module *owner);
--
2.7.4
Boris Brezillon
2018-05-30 14:32:20 UTC
Permalink
Hi Frieder,

On Wed, 30 May 2018 15:14:30 +0200
Post by Frieder Schrempf
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility with the old drivers naming scheme, a function
is added to the SPI mem interface to let controller drivers set a
custom name for the memory.
Name with the old driver: 21e0000.qspi,
or with multiple devices: 21e0000.qspi-0, 21e0000.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
---
drivers/spi/spi-mem.c | 25 +++++++++++++++++++++++++
include/linux/spi/spi-mem.h | 3 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 990770d..5e9af47 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -311,6 +311,31 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
/**
+ * spi_mem_get_name() - Let drivers using the SPI mem interface specify a
+ * custom name for the memory to avoid compatibility
+ * issues with ported drivers.
+ *
+ * When porting (Q)SPI controller drivers from the MTD layer to the SPI
+ * layer, the naming scheme for the memory devices changes. To be able to
+ * keep compatibility with the old drivers naming scheme, this function can
+ * be used to get a custom name from the controller driver.
+ * If no custom name is available, the name of the SPI device is returned.
+ *
+ * Return: a char array that contains the name for the flash memory
+ */
+const char *spi_mem_get_name(struct spi_mem *mem)
+{
+ struct spi_controller *ctlr = mem->spi->controller;
+
+ if (ctlr->mem_ops && ctlr->mem_ops->get_name)
+ return ctlr->mem_ops->get_name(mem);
Looks like your implementation of ->get_name() in the fsl driver is
allocating a new string each time it's called. I guess other
implementations might be forced to do the same, so maybe it's better to
add a ->name field to struct spi_mem and only call ->get_name() once
when the device is probed. Then spi_mem_get_name() can just be
implemented like this:

const char *spi_mem_get_name(struct spi_mem *mem)
{
return mem->name;
}

Regards,

Boris
Post by Frieder Schrempf
+
+ return dev_name(&mem->spi->dev);
+}
+EXPORT_SYMBOL_GPL(spi_mem_get_name);
+
+/**
* spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
* match controller limitations
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 4fa34a2..f1912d3 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -178,6 +178,7 @@ struct spi_controller_mem_ops {
const struct spi_mem_op *op);
int (*exec_op)(struct spi_mem *mem,
const struct spi_mem_op *op);
+ const char *(*get_name)(struct spi_mem *mem);
};
/**
@@ -236,6 +237,8 @@ bool spi_mem_supports_op(struct spi_mem *mem,
int spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op);
+const char *spi_mem_get_name(struct spi_mem *mem);
+
int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
struct module *owner);
Frieder Schrempf
2018-05-30 15:12:18 UTC
Permalink
Hi Boris,
Post by Yogesh Narayan Gaur
Hi Frieder,
On Wed, 30 May 2018 15:14:30 +0200
Post by Frieder Schrempf
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility with the old drivers naming scheme, a function
is added to the SPI mem interface to let controller drivers set a
custom name for the memory.
Name with the old driver: 21e0000.qspi,
or with multiple devices: 21e0000.qspi-0, 21e0000.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
---
drivers/spi/spi-mem.c | 25 +++++++++++++++++++++++++
include/linux/spi/spi-mem.h | 3 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 990770d..5e9af47 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -311,6 +311,31 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
/**
+ * spi_mem_get_name() - Let drivers using the SPI mem interface specify a
+ * custom name for the memory to avoid compatibility
+ * issues with ported drivers.
+ *
+ * When porting (Q)SPI controller drivers from the MTD layer to the SPI
+ * layer, the naming scheme for the memory devices changes. To be able to
+ * keep compatibility with the old drivers naming scheme, this function can
+ * be used to get a custom name from the controller driver.
+ * If no custom name is available, the name of the SPI device is returned.
+ *
+ * Return: a char array that contains the name for the flash memory
+ */
+const char *spi_mem_get_name(struct spi_mem *mem)
+{
+ struct spi_controller *ctlr = mem->spi->controller;
+
+ if (ctlr->mem_ops && ctlr->mem_ops->get_name)
+ return ctlr->mem_ops->get_name(mem);
Looks like your implementation of ->get_name() in the fsl driver is
allocating a new string each time it's called. I guess other
implementations might be forced to do the same, so maybe it's better to
add a ->name field to struct spi_mem and only call ->get_name() once
when the device is probed. Then spi_mem_get_name() can just be
const char *spi_mem_get_name(struct spi_mem *mem)
{
return mem->name;
}
Sounds like a good proposal. I will change that.

Thanks,

Frieder
Post by Yogesh Narayan Gaur
Regards,
Boris
Post by Frieder Schrempf
+
+ return dev_name(&mem->spi->dev);
+}
+EXPORT_SYMBOL_GPL(spi_mem_get_name);
+
+/**
* spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
* match controller limitations
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 4fa34a2..f1912d3 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -178,6 +178,7 @@ struct spi_controller_mem_ops {
const struct spi_mem_op *op);
int (*exec_op)(struct spi_mem *mem,
const struct spi_mem_op *op);
+ const char *(*get_name)(struct spi_mem *mem);
};
/**
@@ -236,6 +237,8 @@ bool spi_mem_supports_op(struct spi_mem *mem,
int spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op);
+const char *spi_mem_get_name(struct spi_mem *mem);
+
int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
struct module *owner);
Frieder Schrempf
2018-05-30 13:14:32 UTC
Permalink
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).

The controller does not support generic SPI messages.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-fsl-qspi.c | 929 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 941 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e62ac32..6de0df5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,17 @@ config SPI_FSL_LPSPI
help
This enables Freescale i.MX LPSPI controllers in master mode.

+config SPI_FSL_QSPI
+ tristate "Freescale QSPI controller"
+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This enables support for the Quad SPI controller in master mode.
+ Up to four flash chips can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages. It only
+ supports the high-level SPI memory interface.
+
config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cb1f437..a8f7fda 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl-dspi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o
+obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
new file mode 100644
index 0000000..c16d070
--- /dev/null
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -0,0 +1,929 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ *
+ * Transition to SPI MEM interface:
+ * Author:
+ * Boris Brezillion <***@bootlin.com>
+ * Frieder Schrempf <***@exceet.de>
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver:
+ * Author: Freescale Semiconductor, Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_qos.h>
+#include <linux/sizes.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#define SEQID_LUT 15
+
+/* Registers used by the driver */
+#define QUADSPI_MCR 0x00
+#define QUADSPI_MCR_RESERVED_MASK (0xF << 16)
+#define QUADSPI_MCR_MDIS_MASK BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
+#define QUADSPI_MCR_END_CFG_MASK (0x3 << 2)
+#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
+
+#define QUADSPI_IPCR 0x08
+#define QUADSPI_IPCR_SEQID_SHIFT 24
+
+#define QUADSPI_BUF3CR 0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
+
+#define QUADSPI_BFGENCR 0x20
+#define QUADSPI_BFGENCR_SEQID_SHIFT 12
+
+#define QUADSPI_BUF0IND 0x30
+#define QUADSPI_BUF1IND 0x34
+#define QUADSPI_BUF2IND 0x38
+#define QUADSPI_SFAR 0x100
+
+#define QUADSPI_SMPR 0x108
+#define QUADSPI_SMPR_DDRSMP_MASK (7 << 16)
+#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
+#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
+#define QUADSPI_SMPR_HSENA_MASK BIT(0)
+
+#define QUADSPI_RBCT 0x110
+#define QUADSPI_RBCT_WMRK_MASK 0x1F
+#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
+
+#define QUADSPI_TBDR 0x154
+
+#define QUADSPI_SR 0x15c
+#define QUADSPI_SR_IP_ACC_MASK BIT(1)
+#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
+
+#define QUADSPI_FR 0x160
+#define QUADSPI_FR_TFF_MASK BIT(0)
+
+#define QUADSPI_SPTRCLR 0x16c
+#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
+#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
+
+#define QUADSPI_SFA1AD 0x180
+#define QUADSPI_SFA2AD 0x184
+#define QUADSPI_SFB1AD 0x188
+#define QUADSPI_SFB2AD 0x18c
+#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
+
+#define QUADSPI_LUTKEY 0x300
+#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
+
+#define QUADSPI_LCKCR 0x304
+#define QUADSPI_LCKER_LOCK BIT(0)
+#define QUADSPI_LCKER_UNLOCK BIT(1)
+
+#define QUADSPI_RSER 0x164
+#define QUADSPI_RSER_TFIE BIT(0)
+
+#define QUADSPI_LUT_BASE 0x310
+#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) (QUADSPI_LUT_BASE + \
+ QUADSPI_LUT_OFFSET + (idx) * 4)
+
+/* Instruction set for the LUT register */
+#define LUT_STOP 0
+#define LUT_CMD 1
+#define LUT_ADDR 2
+#define LUT_DUMMY 3
+#define LUT_MODE 4
+#define LUT_MODE2 5
+#define LUT_MODE4 6
+#define LUT_FSL_READ 7
+#define LUT_FSL_WRITE 8
+#define LUT_JMP_ON_CS 9
+#define LUT_ADDR_DDR 10
+#define LUT_MODE_DDR 11
+#define LUT_MODE2_DDR 12
+#define LUT_MODE4_DDR 13
+#define LUT_FSL_READ_DDR 14
+#define LUT_FSL_WRITE_DDR 15
+#define LUT_DATA_LEARN 16
+
+/*
+ * The PAD definitions for LUT register.
+ *
+ * The pad stands for the number of IO lines [0:3].
+ * For example, the quad read needs four IO lines,
+ * so you should use LUT_PAD(4).
+ */
+#define LUT_PAD(x) (fls(x) - 1)
+
+/*
+ * Macro for constructing the LUT entries with the following
+ * register layout:
+ *
+ * ---------------------------------------------------
+ * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ * ---------------------------------------------------
+ */
+#define LUT_DEF(idx, ins, pad, opr) \
+ ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
+
+/* Controller needs driver to swap endianness */
+#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
+
+/* Controller needs 4x internal clock */
+#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
+
+/*
+ * TKT253890, the controller needs the driver to fill the txfifo with
+ * 16 bytes at least to trigger a data transfer, even though the extra
+ * data won't be transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890 BIT(2)
+
+/* TKT245618, the controller cannot wake up from wait mode */
+#define QUADSPI_QUIRK_TKT245618 BIT(3)
+
+enum fsl_qspi_devtype {
+ FSL_QUADSPI_VYBRID,
+ FSL_QUADSPI_IMX6SX,
+ FSL_QUADSPI_IMX7D,
+ FSL_QUADSPI_IMX6UL,
+ FSL_QUADSPI_LS1021A,
+ FSL_QUADSPI_LS2080A,
+};
+
+struct fsl_qspi_devtype_data {
+ enum fsl_qspi_devtype devtype;
+ unsigned int rxfifo;
+ unsigned int txfifo;
+ unsigned int ahb_buf_size;
+ unsigned int quirks;
+};
+
+static const struct fsl_qspi_devtype_data vybrid_data = {
+ .devtype = FSL_QUADSPI_VYBRID,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
+};
+
+static const struct fsl_qspi_devtype_data imx6sx_data = {
+ .devtype = FSL_QUADSPI_IMX6SX,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
+};
+
+static const struct fsl_qspi_devtype_data imx7d_data = {
+ .devtype = FSL_QUADSPI_IMX7D,
+ .rxfifo = SZ_512,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+};
+
+static const struct fsl_qspi_devtype_data imx6ul_data = {
+ .devtype = FSL_QUADSPI_IMX6UL,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+};
+
+static const struct fsl_qspi_devtype_data ls1021a_data = {
+ .devtype = FSL_QUADSPI_LS1021A,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = 0,
+};
+
+static const struct fsl_qspi_devtype_data ls2080a_data = {
+ .devtype = FSL_QUADSPI_LS2080A,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890,
+};
+
+struct fsl_qspi {
+ void __iomem *iobase;
+ void __iomem *ahb_addr;
+ u32 memmap_phy;
+ struct clk *clk, *clk_en;
+ struct device *dev;
+ struct completion c;
+ const struct fsl_qspi_devtype_data *devtype_data;
+ bool big_endian;
+ struct mutex lock;
+ struct pm_qos_request pm_qos_req;
+ int selected;
+};
+
+static inline int needs_swap_endian(struct fsl_qspi *q)
+{
+ return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
+}
+
+static inline int needs_4x_clock(struct fsl_qspi *q)
+{
+ return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
+}
+
+static inline int needs_fill_txfifo(struct fsl_qspi *q)
+{
+ return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
+}
+
+static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
+{
+ return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
+}
+
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
+{
+ return needs_swap_endian(q) ? __swab32(a) : a;
+}
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The QSPI controller's endianness is independent of
+ * the CPU core's endianness. So far, although the CPU
+ * core is little-endian the QSPI controller can use
+ * big-endian or little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+ if (q->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+ if (q->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
+
+static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
+{
+ struct fsl_qspi *q = dev_id;
+ u32 reg;
+
+ /* clear interrupt */
+ reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+ qspi_writel(q, reg, q->iobase + QUADSPI_FR);
+
+ if (reg & QUADSPI_FR_TFF_MASK)
+ complete(&q->c);
+
+ dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
+ return IRQ_HANDLED;
+}
+
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
+{
+ switch (width) {
+ case 1:
+ case 2:
+ case 4:
+ return 0;
+ }
+
+ return -ENOTSUPP;
+}
+
+static bool fsl_qspi_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ int ret;
+
+ ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
+
+ if (op->addr.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
+
+ if (op->dummy.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
+
+ if (op->data.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
+
+ if (ret)
+ return false;
+
+ /*
+ * The number of instructions needed for the op, needs
+ * to fit into a single LUT entry.
+ */
+ if (op->addr.nbytes +
+ (op->dummy.nbytes ? 1:0) +
+ (op->data.nbytes ? 1:0) > 6)
+ return false;
+
+ /* Max 64 dummy clock cycles supported */
+ if (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)
+ return false;
+
+ /* Max data length, check controller limits and alignment */
+ if (op->data.dir == SPI_MEM_DATA_IN &&
+ (op->data.nbytes > q->devtype_data->ahb_buf_size ||
+ (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
+ !IS_ALIGNED(op->data.nbytes, 8))))
+ return false;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT &&
+ op->data.nbytes > q->devtype_data->txfifo)
+ return false;
+
+ return true;
+}
+
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ u32 lutval[4] = {};
+ int lutidx = 1, i;
+
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+
+ /*
+ * For some unknown reason, using LUT_ADDR doesn't work in some
+ * cases (at least with only one byte long addresses), so
+ * let's use LUT_MODE to write the address bytes one by one
+ */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+ LUT_PAD(op->addr.buswidth),
+ addrbyte);
+ lutidx++;
+ }
+
+ if (op->dummy.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ LUT_PAD(op->dummy.buswidth),
+ op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ lutidx++;
+ }
+
+ if (op->data.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ LUT_FSL_READ : LUT_FSL_WRITE,
+ LUT_PAD(op->data.buswidth),
+ 0);
+ lutidx++;
+ }
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+ /* unlock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+
+ /* fill LUT */
+ for (i = 0; i < ARRAY_SIZE(lutval); i++)
+ qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
+
+ /* lock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+}
+
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
+{
+ int ret;
+
+ ret = clk_prepare_enable(q->clk_en);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(q->clk);
+ if (ret) {
+ clk_disable_unprepare(q->clk_en);
+ return ret;
+ }
+
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
+ return 0;
+}
+
+static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
+{
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_remove_request(&q->pm_qos_req);
+
+ clk_disable_unprepare(q->clk);
+ clk_disable_unprepare(q->clk_en);
+}
+
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
+{
+ unsigned long rate = spi->max_speed_hz;
+ int ret, i;
+ u32 map_addr;
+
+ if (q->selected == spi->chip_select)
+ return;
+
+ /*
+ * In HW there can be a maximum of four chips on two buses with
+ * two chip selects on each bus. We use four chip selects in SW
+ * to differentiate between the four chips.
+ * We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
+ * the chip we want to access.
+ */
+ for (i = 0; i < 4; i++) {
+ if (i < spi->chip_select)
+ map_addr = q->memmap_phy;
+ else
+ map_addr = q->memmap_phy +
+ 2 * q->devtype_data->ahb_buf_size;
+
+ qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
+ }
+
+ if (needs_4x_clock(q))
+ rate *= 4;
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ ret = clk_set_rate(q->clk, rate);
+ if (ret)
+ return;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return;
+
+ q->selected = spi->chip_select;
+}
+
+static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
+{
+ static int seq;
+
+ /*
+ * We want to avoid needing to invalidate the cache by issueing
+ * a reset to the AHB and Serial Flash domain, as this needs
+ * time. So we change the address on each read to trigger an
+ * actual read operation on the flash. The actual address for
+ * the flash memory is set by programming the LUT.
+ */
+ memcpy_fromio(op->data.buf.in,
+ q->ahb_addr +
+ (seq * q->devtype_data->ahb_buf_size),
+ op->data.nbytes);
+
+ seq = seq ? 0 : 1;
+}
+
+static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int i;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = 0;
+
+ memcpy(&val, op->data.buf.out + i,
+ min_t(unsigned int, op->data.nbytes - i, 4));
+
+ val = fsl_qspi_endian_xchg(q, val);
+ qspi_writel(q, val, base + QUADSPI_TBDR);
+ }
+
+ if (needs_fill_txfifo(q)) {
+ for (; i < 16; i += 4)
+ qspi_writel(q, 0, base + QUADSPI_TBDR);
+ }
+}
+
+static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int i;
+ u8 *buf = op->data.buf.in;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+
+ val = fsl_qspi_endian_xchg(q, val);
+
+ memcpy(buf + i, &val,
+ min_t(unsigned int, op->data.nbytes - i, 4));
+ }
+}
+
+static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ init_completion(&q->c);
+
+ /*
+ * Always start the sequence at the same index since we update
+ * the LUT at each exec_op() call. And also specify the DATA
+ * length, since it's has not been specified in the LUT.
+ */
+ qspi_writel(q, op->data.nbytes |
+ (SEQID_LUT << QUADSPI_IPCR_SEQID_SHIFT),
+ base + QUADSPI_IPCR);
+
+ /* Wait for the interrupt. */
+ if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
+ err = -ETIMEDOUT;
+
+ if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ fsl_qspi_read_rxfifo(q, op);
+
+ return err;
+}
+
+static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ mutex_lock(&q->lock);
+
+ /* wait for the controller being ready */
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
+
+ fsl_qspi_select_mem(q, mem->spi);
+
+ qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);
+
+ qspi_writel(q,
+ qspi_readl(q, base + QUADSPI_MCR) |
+ QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+ base + QUADSPI_MCR);
+
+ qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+ base + QUADSPI_SPTRCLR);
+
+ fsl_qspi_prepare_lut(q, op);
+
+ /*
+ * If we have large chunks of data, we read them through the AHB bus
+ * by accessing the mapped memory. In all other cases we use
+ * IP commands to access the flash.
+ */
+ if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+ op->data.dir == SPI_MEM_DATA_IN) {
+ fsl_qspi_read_ahb(q, op);
+ } else {
+ qspi_writel(q,
+ QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+ fsl_qspi_fill_txfifo(q, op);
+
+ err = fsl_qspi_do_op(q, op);
+ }
+
+ mutex_unlock(&q->lock);
+
+ return err;
+}
+
+static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->data.nbytes > q->devtype_data->txfifo)
+ op->data.nbytes = q->devtype_data->txfifo;
+ } else {
+ if (op->data.nbytes > q->devtype_data->ahb_buf_size)
+ op->data.nbytes = q->devtype_data->ahb_buf_size;
+ else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
+ op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
+ }
+
+ return 0;
+}
+
+static int fsl_qspi_default_setup(struct fsl_qspi *q)
+{
+ void __iomem *base = q->iobase;
+ u32 reg;
+ int ret;
+
+ /* disable and unprepare clock to avoid glitch pass to controller */
+ fsl_qspi_clk_disable_unprep(q);
+
+ /* the default frequency, we will change it later if necessary. */
+ ret = clk_set_rate(q->clk, 66000000);
+ if (ret)
+ return ret;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return ret;
+
+ /* Reset the module */
+ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+ base + QUADSPI_MCR);
+ udelay(1);
+
+ /* Disable the module */
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+ base + QUADSPI_MCR);
+
+ reg = qspi_readl(q, base + QUADSPI_SMPR);
+ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
+ | QUADSPI_SMPR_FSPHS_MASK
+ | QUADSPI_SMPR_HSENA_MASK
+ | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+
+ /* We only use the buffer3 for AHB read */
+ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF2IND);
+
+ qspi_writel(q, SEQID_LUT << QUADSPI_BFGENCR_SEQID_SHIFT,
+ q->iobase + QUADSPI_BFGENCR);
+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ ((q->devtype_data->ahb_buf_size / 8) <<
+ QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+
+ q->selected = -1;
+
+ /* Enable the module */
+ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+ base + QUADSPI_MCR);
+
+ /* clear all interrupt status */
+ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
+
+ /* enable the interrupt */
+ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+
+ return 0;
+}
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = &mem->spi->dev;
+ const char *name;
+
+ /*
+ * In order to keep mtdparts compatible with the old MTD driver at
+ * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
+ * platform_device of the controller.
+ */
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
+ }
+
+ return name;
+}
+
+static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
+ .adjust_op_size = fsl_qspi_adjust_op_size,
+ .supports_op = fsl_qspi_supports_op,
+ .exec_op = fsl_qspi_exec_op,
+ .get_name = fsl_qspi_get_name,
+};
+
+static int fsl_qspi_probe(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ struct fsl_qspi *q;
+ int ret;
+
+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
+ if (!ctlr)
+ return -ENOMEM;
+
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
+ SPI_TX_DUAL | SPI_TX_QUAD;
+
+ q = spi_controller_get_devdata(ctlr);
+ q->dev = dev;
+ q->devtype_data = of_device_get_match_data(dev);
+ if (!q->devtype_data) {
+ ret = -ENODEV;
+ goto err_put_ctrl;
+ }
+
+ platform_set_drvdata(pdev, q);
+
+ /* find the resources */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
+ q->iobase = devm_ioremap_resource(dev, res);
+ if (IS_ERR(q->iobase)) {
+ ret = PTR_ERR(q->iobase);
+ goto err_put_ctrl;
+ }
+
+ q->big_endian = of_property_read_bool(np, "big-endian");
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "QuadSPI-memory");
+ q->ahb_addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(q->ahb_addr)) {
+ ret = PTR_ERR(q->ahb_addr);
+ goto err_put_ctrl;
+ }
+
+ q->memmap_phy = res->start;
+
+ /* find the clocks */
+ q->clk_en = devm_clk_get(dev, "qspi_en");
+ if (IS_ERR(q->clk_en)) {
+ ret = PTR_ERR(q->clk_en);
+ goto err_put_ctrl;
+ }
+
+ q->clk = devm_clk_get(dev, "qspi");
+ if (IS_ERR(q->clk)) {
+ ret = PTR_ERR(q->clk);
+ goto err_put_ctrl;
+ }
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ goto err_put_ctrl;
+ }
+
+ /* find the irq */
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "failed to get the irq: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ ret = devm_request_irq(dev, ret,
+ fsl_qspi_irq_handler, 0, pdev->name, q);
+ if (ret) {
+ dev_err(dev, "failed to request irq: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ mutex_init(&q->lock);
+
+ ctlr->bus_num = -1;
+ ctlr->num_chipselect = 4;
+ ctlr->mem_ops = &fsl_qspi_mem_ops;
+
+ fsl_qspi_default_setup(q);
+
+ ctlr->dev.of_node = np;
+
+ ret = spi_register_controller(ctlr);
+ if (ret)
+ goto err_destroy_mutex;
+
+ return 0;
+
+err_destroy_mutex:
+ mutex_destroy(&q->lock);
+
+err_disable_clk:
+ fsl_qspi_clk_disable_unprep(q);
+
+err_put_ctrl:
+ spi_controller_put(ctlr);
+
+ dev_err(dev, "Freescale QuadSPI probe failed\n");
+ return ret;
+}
+
+static int fsl_qspi_remove(struct platform_device *pdev)
+{
+ struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+ /* disable the hardware */
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ mutex_destroy(&q->lock);
+
+ if (q->ahb_addr)
+ iounmap(q->ahb_addr);
+
+ return 0;
+}
+
+static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ return 0;
+}
+
+static int fsl_qspi_resume(struct platform_device *pdev)
+{
+ struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+ fsl_qspi_default_setup(q);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_qspi_dt_ids[] = {
+ { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
+ { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
+ { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
+ { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
+ { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
+ { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
+
+static struct platform_driver fsl_qspi_driver = {
+ .driver = {
+ .name = "fsl-quadspi",
+ .of_match_table = fsl_qspi_dt_ids,
+ },
+ .probe = fsl_qspi_probe,
+ .remove = fsl_qspi_remove,
+ .suspend = fsl_qspi_suspend,
+ .resume = fsl_qspi_resume,
+};
+module_platform_driver(fsl_qspi_driver);
+
+MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
+MODULE_AUTHOR("Freescale Semiconductor Inc.");
+MODULE_AUTHOR("Boris Brezillion <***@bootlin.com>");
+MODULE_AUTHOR("Frieder Schrempf <***@exceet.de>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Yogesh Narayan Gaur
2018-05-30 13:50:51 UTC
Permalink
Hi Frieder,

Thanks for migrating the fsl-quadspi.c driver on the new SPI framework.
This patch is using dynamic LUT approach to create the LUT at run time instead of fixed static LUT as being used in current driver present at mtd/spi-nor/fsl-quadspi.c.
I have pushed the changes for dynamic LUT on mtd/spi-nor/fsl-quadspi.c and v10 has been in review stage.

Request you to please add 'signed-off' mentioned in those patches in this patch, patchwork link is https://patchwork.ozlabs.org/patch/896534/

Thanks
Yogesh Gaur

-----Original Message-----
From: Frieder Schrempf [mailto:***@exceet.de]
Sent: Wednesday, May 30, 2018 6:45 PM
To: linux-***@lists.infradead.org; ***@bootlin.com; linux-***@vger.kernel.org
Cc: ***@infradead.org; ***@gmail.com; ***@gmail.com; ***@nod.at; ***@bootlin.com; ***@kernel.org; David Wolfe <***@nxp.com>; Fabio Estevam <***@nxp.com>; Prabhakar Kushwaha <***@nxp.com>; Yogesh Narayan Gaur <***@nxp.com>; Han Xu <***@nxp.com>; Frieder Schrempf <***@exceet.de>; linux-***@vger.kernel.org
Subject: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash chips (2 buses with 2 CS each).

The controller does not support generic SPI messages.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-fsl-qspi.c | 929 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 941 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e62ac32..6de0df5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,17 @@ config SPI_FSL_LPSPI
help
This enables Freescale i.MX LPSPI controllers in master mode.

+config SPI_FSL_QSPI
+ tristate "Freescale QSPI controller"
+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This enables support for the Quad SPI controller in master mode.
+ Up to four flash chips can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages. It only
+ supports the high-level SPI memory interface.
+
config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cb1f437..a8f7fda 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl-dspi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o
+obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file mode 100644 index 0000000..c16d070
--- /dev/null
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -0,0 +1,929 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ *
+ * Transition to SPI MEM interface:
+ * Author:
+ * Boris Brezillion <***@bootlin.com>
+ * Frieder Schrempf <***@exceet.de>
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver:
+ * Author: Freescale Semiconductor, Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_qos.h>
+#include <linux/sizes.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#define SEQID_LUT 15
+
+/* Registers used by the driver */
+#define QUADSPI_MCR 0x00
+#define QUADSPI_MCR_RESERVED_MASK (0xF << 16)
+#define QUADSPI_MCR_MDIS_MASK BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
+#define QUADSPI_MCR_END_CFG_MASK (0x3 << 2)
+#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
+
+#define QUADSPI_IPCR 0x08
+#define QUADSPI_IPCR_SEQID_SHIFT 24
+
+#define QUADSPI_BUF3CR 0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
+
+#define QUADSPI_BFGENCR 0x20
+#define QUADSPI_BFGENCR_SEQID_SHIFT 12
+
+#define QUADSPI_BUF0IND 0x30
+#define QUADSPI_BUF1IND 0x34
+#define QUADSPI_BUF2IND 0x38
+#define QUADSPI_SFAR 0x100
+
+#define QUADSPI_SMPR 0x108
+#define QUADSPI_SMPR_DDRSMP_MASK (7 << 16)
+#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
+#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
+#define QUADSPI_SMPR_HSENA_MASK BIT(0)
+
+#define QUADSPI_RBCT 0x110
+#define QUADSPI_RBCT_WMRK_MASK 0x1F
+#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
+
+#define QUADSPI_TBDR 0x154
+
+#define QUADSPI_SR 0x15c
+#define QUADSPI_SR_IP_ACC_MASK BIT(1)
+#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
+
+#define QUADSPI_FR 0x160
+#define QUADSPI_FR_TFF_MASK BIT(0)
+
+#define QUADSPI_SPTRCLR 0x16c
+#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
+#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
+
+#define QUADSPI_SFA1AD 0x180
+#define QUADSPI_SFA2AD 0x184
+#define QUADSPI_SFB1AD 0x188
+#define QUADSPI_SFB2AD 0x18c
+#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
+
+#define QUADSPI_LUTKEY 0x300
+#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
+
+#define QUADSPI_LCKCR 0x304
+#define QUADSPI_LCKER_LOCK BIT(0)
+#define QUADSPI_LCKER_UNLOCK BIT(1)
+
+#define QUADSPI_RSER 0x164
+#define QUADSPI_RSER_TFIE BIT(0)
+
+#define QUADSPI_LUT_BASE 0x310
+#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) (QUADSPI_LUT_BASE + \
+ QUADSPI_LUT_OFFSET + (idx) * 4)
+
+/* Instruction set for the LUT register */
+#define LUT_STOP 0
+#define LUT_CMD 1
+#define LUT_ADDR 2
+#define LUT_DUMMY 3
+#define LUT_MODE 4
+#define LUT_MODE2 5
+#define LUT_MODE4 6
+#define LUT_FSL_READ 7
+#define LUT_FSL_WRITE 8
+#define LUT_JMP_ON_CS 9
+#define LUT_ADDR_DDR 10
+#define LUT_MODE_DDR 11
+#define LUT_MODE2_DDR 12
+#define LUT_MODE4_DDR 13
+#define LUT_FSL_READ_DDR 14
+#define LUT_FSL_WRITE_DDR 15
+#define LUT_DATA_LEARN 16
+
+/*
+ * The PAD definitions for LUT register.
+ *
+ * The pad stands for the number of IO lines [0:3].
+ * For example, the quad read needs four IO lines,
+ * so you should use LUT_PAD(4).
+ */
+#define LUT_PAD(x) (fls(x) - 1)
+
+/*
+ * Macro for constructing the LUT entries with the following
+ * register layout:
+ *
+ * ---------------------------------------------------
+ * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ * ---------------------------------------------------
+ */
+#define LUT_DEF(idx, ins, pad, opr) \
+ ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
+
+/* Controller needs driver to swap endianness */
+#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
+
+/* Controller needs 4x internal clock */
+#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
+
+/*
+ * TKT253890, the controller needs the driver to fill the txfifo with
+ * 16 bytes at least to trigger a data transfer, even though the extra
+ * data won't be transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890 BIT(2)
+
+/* TKT245618, the controller cannot wake up from wait mode */
+#define QUADSPI_QUIRK_TKT245618 BIT(3)
+
+enum fsl_qspi_devtype {
+ FSL_QUADSPI_VYBRID,
+ FSL_QUADSPI_IMX6SX,
+ FSL_QUADSPI_IMX7D,
+ FSL_QUADSPI_IMX6UL,
+ FSL_QUADSPI_LS1021A,
+ FSL_QUADSPI_LS2080A,
+};
+
+struct fsl_qspi_devtype_data {
+ enum fsl_qspi_devtype devtype;
+ unsigned int rxfifo;
+ unsigned int txfifo;
+ unsigned int ahb_buf_size;
+ unsigned int quirks;
+};
+
+static const struct fsl_qspi_devtype_data vybrid_data = {
+ .devtype = FSL_QUADSPI_VYBRID,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
+};
+
+static const struct fsl_qspi_devtype_data imx6sx_data = {
+ .devtype = FSL_QUADSPI_IMX6SX,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, };
+
+static const struct fsl_qspi_devtype_data imx7d_data = {
+ .devtype = FSL_QUADSPI_IMX7D,
+ .rxfifo = SZ_512,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK, };
+
+static const struct fsl_qspi_devtype_data imx6ul_data = {
+ .devtype = FSL_QUADSPI_IMX6UL,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK, };
+
+static const struct fsl_qspi_devtype_data ls1021a_data = {
+ .devtype = FSL_QUADSPI_LS1021A,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = 0,
+};
+
+static const struct fsl_qspi_devtype_data ls2080a_data = {
+ .devtype = FSL_QUADSPI_LS2080A,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890,
+};
+
+struct fsl_qspi {
+ void __iomem *iobase;
+ void __iomem *ahb_addr;
+ u32 memmap_phy;
+ struct clk *clk, *clk_en;
+ struct device *dev;
+ struct completion c;
+ const struct fsl_qspi_devtype_data *devtype_data;
+ bool big_endian;
+ struct mutex lock;
+ struct pm_qos_request pm_qos_req;
+ int selected;
+};
+
+static inline int needs_swap_endian(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; }
+
+static inline int needs_4x_clock(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; }
+
+static inline int needs_fill_txfifo(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; }
+
+static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; }
+
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
+ return needs_swap_endian(q) ? __swab32(a) : a; }
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The QSPI controller's endianness is independent of
+ * the CPU core's endianness. So far, although the CPU
+ * core is little-endian the QSPI controller can use
+ * big-endian or little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
+*addr) {
+ if (q->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
+ if (q->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
+
+static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) {
+ struct fsl_qspi *q = dev_id;
+ u32 reg;
+
+ /* clear interrupt */
+ reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+ qspi_writel(q, reg, q->iobase + QUADSPI_FR);
+
+ if (reg & QUADSPI_FR_TFF_MASK)
+ complete(&q->c);
+
+ dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
+ return IRQ_HANDLED;
+}
+
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
+ switch (width) {
+ case 1:
+ case 2:
+ case 4:
+ return 0;
+ }
+
+ return -ENOTSUPP;
+}
+
+static bool fsl_qspi_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ int ret;
+
+ ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
+
+ if (op->addr.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
+
+ if (op->dummy.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
+
+ if (op->data.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
+
+ if (ret)
+ return false;
+
+ /*
+ * The number of instructions needed for the op, needs
+ * to fit into a single LUT entry.
+ */
+ if (op->addr.nbytes +
+ (op->dummy.nbytes ? 1:0) +
+ (op->data.nbytes ? 1:0) > 6)
+ return false;
+
+ /* Max 64 dummy clock cycles supported */
+ if (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)
+ return false;
+
+ /* Max data length, check controller limits and alignment */
+ if (op->data.dir == SPI_MEM_DATA_IN &&
+ (op->data.nbytes > q->devtype_data->ahb_buf_size ||
+ (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
+ !IS_ALIGNED(op->data.nbytes, 8))))
+ return false;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT &&
+ op->data.nbytes > q->devtype_data->txfifo)
+ return false;
+
+ return true;
+}
+
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ u32 lutval[4] = {};
+ int lutidx = 1, i;
+
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+
+ /*
+ * For some unknown reason, using LUT_ADDR doesn't work in some
+ * cases (at least with only one byte long addresses), so
+ * let's use LUT_MODE to write the address bytes one by one
+ */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+ LUT_PAD(op->addr.buswidth),
+ addrbyte);
+ lutidx++;
+ }
+
+ if (op->dummy.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ LUT_PAD(op->dummy.buswidth),
+ op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ lutidx++;
+ }
+
+ if (op->data.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ LUT_FSL_READ : LUT_FSL_WRITE,
+ LUT_PAD(op->data.buswidth),
+ 0);
+ lutidx++;
+ }
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+ /* unlock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+
+ /* fill LUT */
+ for (i = 0; i < ARRAY_SIZE(lutval); i++)
+ qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
+
+ /* lock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
+
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
+ int ret;
+
+ ret = clk_prepare_enable(q->clk_en);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(q->clk);
+ if (ret) {
+ clk_disable_unprepare(q->clk_en);
+ return ret;
+ }
+
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
+ return 0;
+}
+
+static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) {
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_remove_request(&q->pm_qos_req);
+
+ clk_disable_unprepare(q->clk);
+ clk_disable_unprepare(q->clk_en);
+}
+
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device
+*spi) {
+ unsigned long rate = spi->max_speed_hz;
+ int ret, i;
+ u32 map_addr;
+
+ if (q->selected == spi->chip_select)
+ return;
+
+ /*
+ * In HW there can be a maximum of four chips on two buses with
+ * two chip selects on each bus. We use four chip selects in SW
+ * to differentiate between the four chips.
+ * We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
+ * the chip we want to access.
+ */
+ for (i = 0; i < 4; i++) {
+ if (i < spi->chip_select)
+ map_addr = q->memmap_phy;
+ else
+ map_addr = q->memmap_phy +
+ 2 * q->devtype_data->ahb_buf_size;
+
+ qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
+ }
+
+ if (needs_4x_clock(q))
+ rate *= 4;
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ ret = clk_set_rate(q->clk, rate);
+ if (ret)
+ return;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return;
+
+ q->selected = spi->chip_select;
+}
+
+static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
+spi_mem_op *op) {
+ static int seq;
+
+ /*
+ * We want to avoid needing to invalidate the cache by issueing
+ * a reset to the AHB and Serial Flash domain, as this needs
+ * time. So we change the address on each read to trigger an
+ * actual read operation on the flash. The actual address for
+ * the flash memory is set by programming the LUT.
+ */
+ memcpy_fromio(op->data.buf.in,
+ q->ahb_addr +
+ (seq * q->devtype_data->ahb_buf_size),
+ op->data.nbytes);
+
+ seq = seq ? 0 : 1;
+}
+
+static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int i;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = 0;
+
+ memcpy(&val, op->data.buf.out + i,
+ min_t(unsigned int, op->data.nbytes - i, 4));
+
+ val = fsl_qspi_endian_xchg(q, val);
+ qspi_writel(q, val, base + QUADSPI_TBDR);
+ }
+
+ if (needs_fill_txfifo(q)) {
+ for (; i < 16; i += 4)
+ qspi_writel(q, 0, base + QUADSPI_TBDR);
+ }
+}
+
+static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int i;
+ u8 *buf = op->data.buf.in;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+
+ val = fsl_qspi_endian_xchg(q, val);
+
+ memcpy(buf + i, &val,
+ min_t(unsigned int, op->data.nbytes - i, 4));
+ }
+}
+
+static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op
+*op) {
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ init_completion(&q->c);
+
+ /*
+ * Always start the sequence at the same index since we update
+ * the LUT at each exec_op() call. And also specify the DATA
+ * length, since it's has not been specified in the LUT.
+ */
+ qspi_writel(q, op->data.nbytes |
+ (SEQID_LUT << QUADSPI_IPCR_SEQID_SHIFT),
+ base + QUADSPI_IPCR);
+
+ /* Wait for the interrupt. */
+ if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
+ err = -ETIMEDOUT;
+
+ if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ fsl_qspi_read_rxfifo(q, op);
+
+ return err;
+}
+
+static int fsl_qspi_exec_op(struct spi_mem *mem, const struct
+spi_mem_op *op) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ mutex_lock(&q->lock);
+
+ /* wait for the controller being ready */
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
+
+ fsl_qspi_select_mem(q, mem->spi);
+
+ qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);
+
+ qspi_writel(q,
+ qspi_readl(q, base + QUADSPI_MCR) |
+ QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+ base + QUADSPI_MCR);
+
+ qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+ base + QUADSPI_SPTRCLR);
+
+ fsl_qspi_prepare_lut(q, op);
+
+ /*
+ * If we have large chunks of data, we read them through the AHB bus
+ * by accessing the mapped memory. In all other cases we use
+ * IP commands to access the flash.
+ */
+ if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+ op->data.dir == SPI_MEM_DATA_IN) {
+ fsl_qspi_read_ahb(q, op);
+ } else {
+ qspi_writel(q,
+ QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+ fsl_qspi_fill_txfifo(q, op);
+
+ err = fsl_qspi_do_op(q, op);
+ }
+
+ mutex_unlock(&q->lock);
+
+ return err;
+}
+
+static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct
+spi_mem_op *op) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->data.nbytes > q->devtype_data->txfifo)
+ op->data.nbytes = q->devtype_data->txfifo;
+ } else {
+ if (op->data.nbytes > q->devtype_data->ahb_buf_size)
+ op->data.nbytes = q->devtype_data->ahb_buf_size;
+ else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
+ op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
+ }
+
+ return 0;
+}
+
+static int fsl_qspi_default_setup(struct fsl_qspi *q) {
+ void __iomem *base = q->iobase;
+ u32 reg;
+ int ret;
+
+ /* disable and unprepare clock to avoid glitch pass to controller */
+ fsl_qspi_clk_disable_unprep(q);
+
+ /* the default frequency, we will change it later if necessary. */
+ ret = clk_set_rate(q->clk, 66000000);
+ if (ret)
+ return ret;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return ret;
+
+ /* Reset the module */
+ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+ base + QUADSPI_MCR);
+ udelay(1);
+
+ /* Disable the module */
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+ base + QUADSPI_MCR);
+
+ reg = qspi_readl(q, base + QUADSPI_SMPR);
+ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
+ | QUADSPI_SMPR_FSPHS_MASK
+ | QUADSPI_SMPR_HSENA_MASK
+ | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+
+ /* We only use the buffer3 for AHB read */
+ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF2IND);
+
+ qspi_writel(q, SEQID_LUT << QUADSPI_BFGENCR_SEQID_SHIFT,
+ q->iobase + QUADSPI_BFGENCR);
+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ ((q->devtype_data->ahb_buf_size / 8) <<
+ QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+
+ q->selected = -1;
+
+ /* Enable the module */
+ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+ base + QUADSPI_MCR);
+
+ /* clear all interrupt status */
+ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
+
+ /* enable the interrupt */
+ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+
+ return 0;
+}
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = &mem->spi->dev;
+ const char *name;
+
+ /*
+ * In order to keep mtdparts compatible with the old MTD driver at
+ * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
+ * platform_device of the controller.
+ */
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
+ }
+
+ return name;
+}
+
+static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
+ .adjust_op_size = fsl_qspi_adjust_op_size,
+ .supports_op = fsl_qspi_supports_op,
+ .exec_op = fsl_qspi_exec_op,
+ .get_name = fsl_qspi_get_name,
+};
+
+static int fsl_qspi_probe(struct platform_device *pdev) {
+ struct spi_controller *ctlr;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ struct fsl_qspi *q;
+ int ret;
+
+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
+ if (!ctlr)
+ return -ENOMEM;
+
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
+ SPI_TX_DUAL | SPI_TX_QUAD;
+
+ q = spi_controller_get_devdata(ctlr);
+ q->dev = dev;
+ q->devtype_data = of_device_get_match_data(dev);
+ if (!q->devtype_data) {
+ ret = -ENODEV;
+ goto err_put_ctrl;
+ }
+
+ platform_set_drvdata(pdev, q);
+
+ /* find the resources */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
+ q->iobase = devm_ioremap_resource(dev, res);
+ if (IS_ERR(q->iobase)) {
+ ret = PTR_ERR(q->iobase);
+ goto err_put_ctrl;
+ }
+
+ q->big_endian = of_property_read_bool(np, "big-endian");
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "QuadSPI-memory");
+ q->ahb_addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(q->ahb_addr)) {
+ ret = PTR_ERR(q->ahb_addr);
+ goto err_put_ctrl;
+ }
+
+ q->memmap_phy = res->start;
+
+ /* find the clocks */
+ q->clk_en = devm_clk_get(dev, "qspi_en");
+ if (IS_ERR(q->clk_en)) {
+ ret = PTR_ERR(q->clk_en);
+ goto err_put_ctrl;
+ }
+
+ q->clk = devm_clk_get(dev, "qspi");
+ if (IS_ERR(q->clk)) {
+ ret = PTR_ERR(q->clk);
+ goto err_put_ctrl;
+ }
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ goto err_put_ctrl;
+ }
+
+ /* find the irq */
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "failed to get the irq: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ ret = devm_request_irq(dev, ret,
+ fsl_qspi_irq_handler, 0, pdev->name, q);
+ if (ret) {
+ dev_err(dev, "failed to request irq: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ mutex_init(&q->lock);
+
+ ctlr->bus_num = -1;
+ ctlr->num_chipselect = 4;
+ ctlr->mem_ops = &fsl_qspi_mem_ops;
+
+ fsl_qspi_default_setup(q);
+
+ ctlr->dev.of_node = np;
+
+ ret = spi_register_controller(ctlr);
+ if (ret)
+ goto err_destroy_mutex;
+
+ return 0;
+
+err_destroy_mutex:
+ mutex_destroy(&q->lock);
+
+err_disable_clk:
+ fsl_qspi_clk_disable_unprep(q);
+
+err_put_ctrl:
+ spi_controller_put(ctlr);
+
+ dev_err(dev, "Freescale QuadSPI probe failed\n");
+ return ret;
+}
+
+static int fsl_qspi_remove(struct platform_device *pdev) {
+ struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+ /* disable the hardware */
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ mutex_destroy(&q->lock);
+
+ if (q->ahb_addr)
+ iounmap(q->ahb_addr);
+
+ return 0;
+}
+
+static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t
+state) {
+ return 0;
+}
+
+static int fsl_qspi_resume(struct platform_device *pdev) {
+ struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+ fsl_qspi_default_setup(q);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_qspi_dt_ids[] = {
+ { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
+ { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
+ { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
+ { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
+ { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
+ { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
+
+static struct platform_driver fsl_qspi_driver = {
+ .driver = {
+ .name = "fsl-quadspi",
+ .of_match_table = fsl_qspi_dt_ids,
+ },
+ .probe = fsl_qspi_probe,
+ .remove = fsl_qspi_remove,
+ .suspend = fsl_qspi_suspend,
+ .resume = fsl_qspi_resume,
+};
+module_platform_driver(fsl_qspi_driver);
+
+MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
+MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_AUTHOR("Boris
+Brezillion <***@bootlin.com>"); MODULE_AUTHOR("Frieder
+Schrempf <***@exceet.de>"); MODULE_LICENSE("GPL v2");
--
2.7.4
Boris Brezillon
2018-05-30 14:24:39 UTC
Permalink
Hi Yogesh,

On Wed, 30 May 2018 13:50:51 +0000
Post by Yogesh Narayan Gaur
Hi Frieder,
Thanks for migrating the fsl-quadspi.c driver on the new SPI
framework. This patch is using dynamic LUT approach to create the LUT
at run time instead of fixed static LUT as being used in current
driver present at mtd/spi-nor/fsl-quadspi.c. I have pushed the
changes for dynamic LUT on mtd/spi-nor/fsl-quadspi.c and v10 has been
in review stage.
Request you to please add 'signed-off' mentioned in those patches in
this patch, patchwork link is
https://patchwork.ozlabs.org/patch/896534/
First, I'd like to state that this work has not been based on your
dynamic LUT code, and I actually asked you to adapt your code to match
the way we were handling it in the new driver (which at that time was
still under development). Then, even if you want to be cited as one of
the author of the new code, SoB tag is not the right way to do it (see
[1] for an explanation on when SoB should be added). Instead, you
should add your name in the copyright header and maybe be add a
MODULE_AUTHOR():

/*
* Copyright ...
* ...
* Authors:
* ...
* Yogesh Narayan Gaur <***@nxp.com>
*/

...

MODULE_AUTHOR("Yogesh Narayan Gaur <***@nxp.com>");

Regards,

Boris

[1]https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L429
Frieder Schrempf
2018-06-01 09:14:52 UTC
Permalink
Hi Yogesh,
Post by Boris Brezillon
Hi Yogesh,
On Wed, 30 May 2018 13:50:51 +0000
Post by Yogesh Narayan Gaur
Hi Frieder,
Thanks for migrating the fsl-quadspi.c driver on the new SPI
framework. This patch is using dynamic LUT approach to create the LUT
at run time instead of fixed static LUT as being used in current
driver present at mtd/spi-nor/fsl-quadspi.c. I have pushed the
changes for dynamic LUT on mtd/spi-nor/fsl-quadspi.c and v10 has been
in review stage.
Request you to please add 'signed-off' mentioned in those patches in
this patch, patchwork link is
https://patchwork.ozlabs.org/patch/896534/
So for reasons already given by Boris, I won't add your S-o-b tags. But
I can add your name (and that of Suresh Gupta?) to the file header and
as MODULE_AUTHOR in the next version.

Regards,

Frieder
Post by Boris Brezillon
First, I'd like to state that this work has not been based on your
dynamic LUT code, and I actually asked you to adapt your code to match
the way we were handling it in the new driver (which at that time was
still under development). Then, even if you want to be cited as one of
the author of the new code, SoB tag is not the right way to do it (see
[1] for an explanation on when SoB should be added). Instead, you
should add your name in the copyright header and maybe be add a
/*
* Copyright ...
* ...
* ...
*/
...
Regards,
Boris
[1]https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L429
Boris Brezillon
2018-05-30 14:58:16 UTC
Permalink
Hi Frieder,

On Wed, 30 May 2018 15:14:32 +0200
Post by Frieder Schrempf
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = &mem->spi->dev;
+ const char *name;
+
+ /*
+ * In order to keep mtdparts compatible with the old MTD driver at
+ * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
+ * platform_device of the controller.
+ */
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
Hm, not sure that's what we want. We should probably fail when the
allocation fails.

How about letting ->get_name() return an error pointer or NULL in case
of error. With the other I made suggestion in my review of patch 1
(calling ->get_name() at probe time) you could refuse to probe the
device when ->get_name() fails.
Post by Frieder Schrempf
+ }
+
+ return name;
+}
+
Regards,

Boris
Frieder Schrempf
2018-05-30 15:13:44 UTC
Permalink
Hi Boris,
Post by Yogesh Narayan Gaur
Hi Frieder,
On Wed, 30 May 2018 15:14:32 +0200
Post by Frieder Schrempf
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = &mem->spi->dev;
+ const char *name;
+
+ /*
+ * In order to keep mtdparts compatible with the old MTD driver at
+ * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
+ * platform_device of the controller.
+ */
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
Hm, not sure that's what we want. We should probably fail when the
allocation fails.
Right, we should definitely fail when the allocation fails.
Post by Yogesh Narayan Gaur
How about letting ->get_name() return an error pointer or NULL in case
of error. With the other I made suggestion in my review of patch 1
(calling ->get_name() at probe time) you could refuse to probe the
device when ->get_name() fails.
Ok, I will change that.

Thanks,

Frieder
Post by Yogesh Narayan Gaur
Post by Frieder Schrempf
+ }
+
+ return name;
+}
+
Regards,
Boris
Yogesh Narayan Gaur
2018-06-08 11:54:12 UTC
Permalink
Hi Frieder,

I have tried to validate your patch on fsl,ls2080a target having 2 Spansion NOR flash, S25FS512S, as slave device.
Below are my observations:

Observation 1:
In Linux boot logs after driver probing is successful, getting below log messages
[ 1.435986] m25p80 spi0.0: found s25fl512s, expected m25p80
[ 1.441564] m25p80 spi0.0: s25fl512s (65536 Kbytes)
[ 1.446972] m25p80 spi0.1: found s25fl512s, expected m25p80
[ 1.452548] m25p80 spi0.1: s25fl512s (65536 Kbytes)

IMHO, we need to correct message as 'found s25fl512s, expected m25p80' as final underlying connected flash device is s25fl512s.

Observation 2:
I have observed data sanity issue after performing read/write operations using MTD interface. Explained below

root:~# mtd_debug erase /dev/mtd0 0x1000000 0x40000
Erased 262144 bytes from address 0x01000000 in flash --> Erase at address 0x1000000 of erase size 0x40000
root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
Copied 256 bytes from address 0x00000000 in flash to rp --> Read 0x100 bytes from flash from address 0x0 in file rp
root:~# mtd_debug write /dev/mtd0 0x1000000 0x100 rp
Copied 256 bytes from rp to address 0x01000000 in flash --> Write 0x100 bytes to flash address 0x1000000 from file rp
root:~# mtd_debug read /dev/mtd0 0x1000000 0x100 wp
Copied 256 bytes from address 0x01000000 in flash to wp --> Read 0x100 bytes from flash from address 0x1000000 in file wp
root:~# diff rp wp --> compare both rp and wp files, if they are different output comes on console stating file are different
Files rp and wp differ
root:~# hexdump wp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 ffff ffff ffff ffff ffff ffff ffff ffff
*
0000100
root:~# hexdump rp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 2403 0000 0000 0000 0000 0000 0000 0000
0000050 0000 0000 0000 0000 0000 0000 0000 0000
*
0000070 0011 0000 09e7 0000 0000 4411 9555 0050
0000080 0000 0000 0000 0000 f9bc afa1 0404 31e0
0000090 0000 0000 0400 31e0 0000 2010 08dc 31eb
00000a0 2880 0050 1300 31eb 4e20 8010 0000 80ff
00000b0 0000 0000 beef dead beef dead beef dead
00000c0 beef dead beef dead beef dead beef dead
*
0000100
root:~#

In hexdump output of the file which being read from address 0x1000000,wp, it can be observed that only first 64 bytes (0x40) are written on the flash.

Observation 3:
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.

In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
***@ls1012ardb:~# cat /proc/mtd
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"

***@ls1012ardb:~# mkdir /media/ram ; flash_eraseall /dev/mtd3
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
Erasing 256 Kibyte @ 0 -- 0 % complete [ 18.299929] random: crng init done
Erasing 256 Kibyte @ 2dc0000 -- 100 % complete
***@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/

This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0000: 0x2886 instead
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0008: 0xb10f instead

If I remove this patch series and check with older implementation, JFFS2 mounting is working fine.

Observation 4:
With previous driver, we can read content of flash directly using devmem command
Like devmem 0x20000000 "Flash is connected at this Quad-SPI address"

But with new driver devmem interface reporting in-correct value.


Few other comments inline.

--
Regards,
Yogesh Gaur

-----Original Message-----
From: Frieder Schrempf [mailto:***@exceet.de]
Sent: Wednesday, May 30, 2018 6:45 PM
To: linux-***@lists.infradead.org; ***@bootlin.com; linux-***@vger.kernel.org
Cc: ***@infradead.org; ***@gmail.com; ***@gmail.com; ***@nod.at; ***@bootlin.com; ***@kernel.org; David Wolfe <***@nxp.com>; Fabio Estevam <***@nxp.com>; Prabhakar Kushwaha <***@nxp.com>; Yogesh Narayan Gaur <***@nxp.com>; Han Xu <***@nxp.com>; Frieder Schrempf <***@exceet.de>; linux-***@vger.kernel.org
Subject: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash chips (2 buses with 2 CS each).

The controller does not support generic SPI messages.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-fsl-qspi.c | 929 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 941 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e62ac32..6de0df5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,17 @@ config SPI_FSL_LPSPI
help
This enables Freescale i.MX LPSPI controllers in master mode.

+config SPI_FSL_QSPI
+ tristate "Freescale QSPI controller"
+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This enables support for the Quad SPI controller in master mode.
+ Up to four flash chips can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages. It only
+ supports the high-level SPI memory interface.
+
config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cb1f437..a8f7fda 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl-dspi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o
+obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file mode 100644 index 0000000..c16d070
--- /dev/null
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -0,0 +1,929 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ *
+ * Transition to SPI MEM interface:
+ * Author:
+ * Boris Brezillion <***@bootlin.com>
+ * Frieder Schrempf <***@exceet.de>
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver:
+ * Author: Freescale Semiconductor, Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_qos.h>
+#include <linux/sizes.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#define SEQID_LUT 15
+
+/* Registers used by the driver */
+#define QUADSPI_MCR 0x00
+#define QUADSPI_MCR_RESERVED_MASK (0xF << 16)
+#define QUADSPI_MCR_MDIS_MASK BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
+#define QUADSPI_MCR_END_CFG_MASK (0x3 << 2)
+#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
+
+#define QUADSPI_IPCR 0x08
+#define QUADSPI_IPCR_SEQID_SHIFT 24
+
+#define QUADSPI_BUF3CR 0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
+
+#define QUADSPI_BFGENCR 0x20
+#define QUADSPI_BFGENCR_SEQID_SHIFT 12
+
+#define QUADSPI_BUF0IND 0x30
+#define QUADSPI_BUF1IND 0x34
+#define QUADSPI_BUF2IND 0x38
+#define QUADSPI_SFAR 0x100
+
+#define QUADSPI_SMPR 0x108
+#define QUADSPI_SMPR_DDRSMP_MASK (7 << 16)
+#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
+#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
+#define QUADSPI_SMPR_HSENA_MASK BIT(0)
+
+#define QUADSPI_RBCT 0x110
+#define QUADSPI_RBCT_WMRK_MASK 0x1F
+#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
+
+#define QUADSPI_TBDR 0x154
+
+#define QUADSPI_SR 0x15c
+#define QUADSPI_SR_IP_ACC_MASK BIT(1)
+#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
+
+#define QUADSPI_FR 0x160
+#define QUADSPI_FR_TFF_MASK BIT(0)
+
+#define QUADSPI_SPTRCLR 0x16c
+#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
+#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
+
+#define QUADSPI_SFA1AD 0x180
+#define QUADSPI_SFA2AD 0x184
+#define QUADSPI_SFB1AD 0x188
+#define QUADSPI_SFB2AD 0x18c
+#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
+
+#define QUADSPI_LUTKEY 0x300
+#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
+
+#define QUADSPI_LCKCR 0x304
+#define QUADSPI_LCKER_LOCK BIT(0)
+#define QUADSPI_LCKER_UNLOCK BIT(1)
+
+#define QUADSPI_RSER 0x164
+#define QUADSPI_RSER_TFIE BIT(0)
+
+#define QUADSPI_LUT_BASE 0x310
+#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) (QUADSPI_LUT_BASE + \
+ QUADSPI_LUT_OFFSET + (idx) * 4)
+
+/* Instruction set for the LUT register */
+#define LUT_STOP 0
+#define LUT_CMD 1
+#define LUT_ADDR 2
+#define LUT_DUMMY 3
+#define LUT_MODE 4
+#define LUT_MODE2 5
+#define LUT_MODE4 6
+#define LUT_FSL_READ 7
+#define LUT_FSL_WRITE 8
+#define LUT_JMP_ON_CS 9
+#define LUT_ADDR_DDR 10
+#define LUT_MODE_DDR 11
+#define LUT_MODE2_DDR 12
+#define LUT_MODE4_DDR 13
+#define LUT_FSL_READ_DDR 14
+#define LUT_FSL_WRITE_DDR 15
+#define LUT_DATA_LEARN 16
+
+/*
+ * The PAD definitions for LUT register.
+ *
+ * The pad stands for the number of IO lines [0:3].
+ * For example, the quad read needs four IO lines,
+ * so you should use LUT_PAD(4).
+ */
+#define LUT_PAD(x) (fls(x) - 1)
+
+/*
+ * Macro for constructing the LUT entries with the following
+ * register layout:
+ *
+ * ---------------------------------------------------
+ * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ * ---------------------------------------------------
+ */
+#define LUT_DEF(idx, ins, pad, opr) \
+ ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
+
+/* Controller needs driver to swap endianness */
+#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
+
+/* Controller needs 4x internal clock */
+#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
+
+/*
+ * TKT253890, the controller needs the driver to fill the txfifo with
+ * 16 bytes at least to trigger a data transfer, even though the extra
+ * data won't be transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890 BIT(2)
+
+/* TKT245618, the controller cannot wake up from wait mode */
+#define QUADSPI_QUIRK_TKT245618 BIT(3)
+
+enum fsl_qspi_devtype {
+ FSL_QUADSPI_VYBRID,
+ FSL_QUADSPI_IMX6SX,
+ FSL_QUADSPI_IMX7D,
+ FSL_QUADSPI_IMX6UL,
+ FSL_QUADSPI_LS1021A,
+ FSL_QUADSPI_LS2080A,
+};
+
+struct fsl_qspi_devtype_data {
+ enum fsl_qspi_devtype devtype;
+ unsigned int rxfifo;
+ unsigned int txfifo;
+ unsigned int ahb_buf_size;
+ unsigned int quirks;
+};
+
+static const struct fsl_qspi_devtype_data vybrid_data = {
+ .devtype = FSL_QUADSPI_VYBRID,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
+};
+
+static const struct fsl_qspi_devtype_data imx6sx_data = {
+ .devtype = FSL_QUADSPI_IMX6SX,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, };
+
+static const struct fsl_qspi_devtype_data imx7d_data = {
+ .devtype = FSL_QUADSPI_IMX7D,
+ .rxfifo = SZ_512,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK, };
+
+static const struct fsl_qspi_devtype_data imx6ul_data = {
+ .devtype = FSL_QUADSPI_IMX6UL,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_512,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK, };

Closing brace should be on next line for all above entries.

+
+static const struct fsl_qspi_devtype_data ls1021a_data = {
+ .devtype = FSL_QUADSPI_LS1021A,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = 0,
+};
+
+static const struct fsl_qspi_devtype_data ls2080a_data = {
+ .devtype = FSL_QUADSPI_LS2080A,
+ .rxfifo = SZ_128,
+ .txfifo = SZ_64,
+ .ahb_buf_size = SZ_1K,
+ .quirks = QUADSPI_QUIRK_TKT253890,
+};
+
+struct fsl_qspi {
+ void __iomem *iobase;
+ void __iomem *ahb_addr;
+ u32 memmap_phy;
+ struct clk *clk, *clk_en;
+ struct device *dev;
+ struct completion c;
+ const struct fsl_qspi_devtype_data *devtype_data;
+ bool big_endian;
+ struct mutex lock;
+ struct pm_qos_request pm_qos_req;
+ int selected;
+};
+
+static inline int needs_swap_endian(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; }
+
+static inline int needs_4x_clock(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; }
+
+static inline int needs_fill_txfifo(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; }
+
+static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) {
+ return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; }
+
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
+ return needs_swap_endian(q) ? __swab32(a) : a; }
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The QSPI controller's endianness is independent of
+ * the CPU core's endianness. So far, although the CPU
+ * core is little-endian the QSPI controller can use
+ * big-endian or little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
+*addr) {
+ if (q->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
+ if (q->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
+
+static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) {
+ struct fsl_qspi *q = dev_id;
+ u32 reg;
+
+ /* clear interrupt */
+ reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+ qspi_writel(q, reg, q->iobase + QUADSPI_FR);
+
+ if (reg & QUADSPI_FR_TFF_MASK)
+ complete(&q->c);
+
+ dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
+ return IRQ_HANDLED;
+}
+
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
+ switch (width) {
+ case 1:
+ case 2:
+ case 4:
+ return 0;
+ }
+
+ return -ENOTSUPP;
+}
+
+static bool fsl_qspi_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ int ret;
+
+ ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
+
+ if (op->addr.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
+
+ if (op->dummy.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
+
+ if (op->data.nbytes)
+ ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
+
+ if (ret)
+ return false;
+
+ /*
+ * The number of instructions needed for the op, needs
+ * to fit into a single LUT entry.
+ */
+ if (op->addr.nbytes +
+ (op->dummy.nbytes ? 1:0) +
+ (op->data.nbytes ? 1:0) > 6)
+ return false;
+
+ /* Max 64 dummy clock cycles supported */
+ if (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)
+ return false;
+
+ /* Max data length, check controller limits and alignment */
+ if (op->data.dir == SPI_MEM_DATA_IN &&
+ (op->data.nbytes > q->devtype_data->ahb_buf_size ||
+ (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
+ !IS_ALIGNED(op->data.nbytes, 8))))
+ return false;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT &&
+ op->data.nbytes > q->devtype_data->txfifo)
+ return false;
+
+ return true;
+}
+
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ u32 lutval[4] = {};
+ int lutidx = 1, i;
+
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+
+ /*
+ * For some unknown reason, using LUT_ADDR doesn't work in some
+ * cases (at least with only one byte long addresses), so
+ * let's use LUT_MODE to write the address bytes one by one
+ */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+ LUT_PAD(op->addr.buswidth),
+ addrbyte);
+ lutidx++;
+ }
+

For ADDR filling in LUT we should use LUT_ADDR only, needs to find out the reason for the issue and we shouldn't use LUT_MODE here.
I have few more comments regarding same, mentioned below.

+ if (op->dummy.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ LUT_PAD(op->dummy.buswidth),
+ op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ lutidx++;
+ }
+
+ if (op->data.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ LUT_FSL_READ : LUT_FSL_WRITE,
+ LUT_PAD(op->data.buswidth),
+ 0);
+ lutidx++;
+ }
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+ /* unlock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+
+ /* fill LUT */
+ for (i = 0; i < ARRAY_SIZE(lutval); i++)
+ qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
+
+ /* lock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
+
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
+ int ret;
+
+ ret = clk_prepare_enable(q->clk_en);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(q->clk);
+ if (ret) {
+ clk_disable_unprepare(q->clk_en);
+ return ret;
+ }
+
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
+ return 0;
+}
+
+static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) {
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_remove_request(&q->pm_qos_req);
+
+ clk_disable_unprepare(q->clk);
+ clk_disable_unprepare(q->clk_en);
+}
+
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device
+*spi) {
+ unsigned long rate = spi->max_speed_hz;
+ int ret, i;
+ u32 map_addr;
+
+ if (q->selected == spi->chip_select)
+ return;
+
+ /*
+ * In HW there can be a maximum of four chips on two buses with
+ * two chip selects on each bus. We use four chip selects in SW
+ * to differentiate between the four chips.
+ * We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
+ * the chip we want to access.
+ */
+ for (i = 0; i < 4; i++) {
+ if (i < spi->chip_select)
+ map_addr = q->memmap_phy;
+ else
+ map_addr = q->memmap_phy +
+ 2 * q->devtype_data->ahb_buf_size;
+
+ qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
+ }
+
+ if (needs_4x_clock(q))
+ rate *= 4;
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ ret = clk_set_rate(q->clk, rate);
+ if (ret)
+ return;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return;
+
+ q->selected = spi->chip_select;
+}
+
+static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
+spi_mem_op *op) {
+ static int seq;
+
+ /*
+ * We want to avoid needing to invalidate the cache by issueing
+ * a reset to the AHB and Serial Flash domain, as this needs
+ * time. So we change the address on each read to trigger an
+ * actual read operation on the flash. The actual address for
+ * the flash memory is set by programming the LUT.
+ */
+ memcpy_fromio(op->data.buf.in,
+ q->ahb_addr +
+ (seq * q->devtype_data->ahb_buf_size),
+ op->data.nbytes);
+
+ seq = seq ? 0 : 1;
+}
+
+static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int i;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = 0;
+
+ memcpy(&val, op->data.buf.out + i,
+ min_t(unsigned int, op->data.nbytes - i, 4));
+
+ val = fsl_qspi_endian_xchg(q, val);
+ qspi_writel(q, val, base + QUADSPI_TBDR);
+ }
+
+ if (needs_fill_txfifo(q)) {
+ for (; i < 16; i += 4)
+ qspi_writel(q, 0, base + QUADSPI_TBDR);
+ }
+}
+
+static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ int i;
+ u8 *buf = op->data.buf.in;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+
+ val = fsl_qspi_endian_xchg(q, val);
+
+ memcpy(buf + i, &val,
+ min_t(unsigned int, op->data.nbytes - i, 4));
+ }
+}
+
+static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op
+*op) {
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ init_completion(&q->c);
+
+ /*
+ * Always start the sequence at the same index since we update
+ * the LUT at each exec_op() call. And also specify the DATA
+ * length, since it's has not been specified in the LUT.
+ */
+ qspi_writel(q, op->data.nbytes |
+ (SEQID_LUT << QUADSPI_IPCR_SEQID_SHIFT),
+ base + QUADSPI_IPCR);
+
+ /* Wait for the interrupt. */
+ if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
+ err = -ETIMEDOUT;
+
+ if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ fsl_qspi_read_rxfifo(q, op);
+
+ return err;
+}
+
+static int fsl_qspi_exec_op(struct spi_mem *mem, const struct
+spi_mem_op *op) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ mutex_lock(&q->lock);
+
+ /* wait for the controller being ready */
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
+
+ fsl_qspi_select_mem(q, mem->spi);
+
+ qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);

SFAR should have the actual address where we are doing operation.

For e.g. If reading from flash-0 offset 0x100000 than SFAR should have address as 0x20100000.
As for 'read/write' request 'from/to' respectively been saved in struct spi_mem_op [op.val] this should be added to q->memmap_phy.

In LUT preparation for ADDR, we should use ADDR_WIDTH as 3-byte or 4-byte addressing only.
Start address should be saved in SFAR register.

+
+ qspi_writel(q,
+ qspi_readl(q, base + QUADSPI_MCR) |
+ QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+ base + QUADSPI_MCR);
+
+ qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+ base + QUADSPI_SPTRCLR);
+
+ fsl_qspi_prepare_lut(q, op);
+
+ /*
+ * If we have large chunks of data, we read them through the AHB bus
+ * by accessing the mapped memory. In all other cases we use
+ * IP commands to access the flash.
+ */
+ if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+ op->data.dir == SPI_MEM_DATA_IN) {
+ fsl_qspi_read_ahb(q, op);
+ } else {
+ qspi_writel(q,
+ QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+ fsl_qspi_fill_txfifo(q, op);
+
+ err = fsl_qspi_do_op(q, op);
+ }
+
+ mutex_unlock(&q->lock);
+
+ return err;
+}
+
+static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct
+spi_mem_op *op) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->data.nbytes > q->devtype_data->txfifo)
+ op->data.nbytes = q->devtype_data->txfifo;
+ } else {
+ if (op->data.nbytes > q->devtype_data->ahb_buf_size)
+ op->data.nbytes = q->devtype_data->ahb_buf_size;
+ else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
+ op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
+ }
+
+ return 0;
+}
+
+static int fsl_qspi_default_setup(struct fsl_qspi *q) {
+ void __iomem *base = q->iobase;
+ u32 reg;
+ int ret;
+
+ /* disable and unprepare clock to avoid glitch pass to controller */
+ fsl_qspi_clk_disable_unprep(q);
+
+ /* the default frequency, we will change it later if necessary. */
+ ret = clk_set_rate(q->clk, 66000000);
+ if (ret)
+ return ret;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return ret;
+
+ /* Reset the module */
+ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+ base + QUADSPI_MCR);
+ udelay(1);
+
+ /* Disable the module */
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+ base + QUADSPI_MCR);
+
+ reg = qspi_readl(q, base + QUADSPI_SMPR);
+ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
+ | QUADSPI_SMPR_FSPHS_MASK
+ | QUADSPI_SMPR_HSENA_MASK
+ | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+
+ /* We only use the buffer3 for AHB read */
+ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF2IND);
+
+ qspi_writel(q, SEQID_LUT << QUADSPI_BFGENCR_SEQID_SHIFT,
+ q->iobase + QUADSPI_BFGENCR);
+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ ((q->devtype_data->ahb_buf_size / 8) <<
+ QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+
+ q->selected = -1;
+
+ /* Enable the module */
+ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+ base + QUADSPI_MCR);
+
+ /* clear all interrupt status */
+ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
+
+ /* enable the interrupt */
+ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+
+ return 0;
+}
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = &mem->spi->dev;
+ const char *name;
+
+ /*
+ * In order to keep mtdparts compatible with the old MTD driver at
+ * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
+ * platform_device of the controller.
+ */
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
+ }
+
+ return name;
+}
+
+static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
+ .adjust_op_size = fsl_qspi_adjust_op_size,
+ .supports_op = fsl_qspi_supports_op,
+ .exec_op = fsl_qspi_exec_op,
+ .get_name = fsl_qspi_get_name,
+};
+
+static int fsl_qspi_probe(struct platform_device *pdev) {
+ struct spi_controller *ctlr;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ struct fsl_qspi *q;
+ int ret;
+
+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
+ if (!ctlr)
+ return -ENOMEM;
+
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
+ SPI_TX_DUAL | SPI_TX_QUAD;
+
+ q = spi_controller_get_devdata(ctlr);
+ q->dev = dev;
+ q->devtype_data = of_device_get_match_data(dev);
+ if (!q->devtype_data) {
+ ret = -ENODEV;
+ goto err_put_ctrl;
+ }
+
+ platform_set_drvdata(pdev, q);
+
+ /* find the resources */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
+ q->iobase = devm_ioremap_resource(dev, res);
+ if (IS_ERR(q->iobase)) {
+ ret = PTR_ERR(q->iobase);
+ goto err_put_ctrl;
+ }
+
+ q->big_endian = of_property_read_bool(np, "big-endian");
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "QuadSPI-memory");
+ q->ahb_addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(q->ahb_addr)) {
+ ret = PTR_ERR(q->ahb_addr);
+ goto err_put_ctrl;
+ }
+
+ q->memmap_phy = res->start;
+
+ /* find the clocks */
+ q->clk_en = devm_clk_get(dev, "qspi_en");
+ if (IS_ERR(q->clk_en)) {
+ ret = PTR_ERR(q->clk_en);
+ goto err_put_ctrl;
+ }
+
+ q->clk = devm_clk_get(dev, "qspi");
+ if (IS_ERR(q->clk)) {
+ ret = PTR_ERR(q->clk);
+ goto err_put_ctrl;
+ }
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ goto err_put_ctrl;
+ }
+
+ /* find the irq */
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "failed to get the irq: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ ret = devm_request_irq(dev, ret,
+ fsl_qspi_irq_handler, 0, pdev->name, q);
+ if (ret) {
+ dev_err(dev, "failed to request irq: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ mutex_init(&q->lock);
+
+ ctlr->bus_num = -1;
+ ctlr->num_chipselect = 4;
+ ctlr->mem_ops = &fsl_qspi_mem_ops;
+
+ fsl_qspi_default_setup(q);
+
+ ctlr->dev.of_node = np;
+
+ ret = spi_register_controller(ctlr);
+ if (ret)
+ goto err_destroy_mutex;
+
+ return 0;
+
+err_destroy_mutex:
+ mutex_destroy(&q->lock);
+
+err_disable_clk:
+ fsl_qspi_clk_disable_unprep(q);
+
+err_put_ctrl:
+ spi_controller_put(ctlr);
+
+ dev_err(dev, "Freescale QuadSPI probe failed\n");
+ return ret;
+}
+
+static int fsl_qspi_remove(struct platform_device *pdev) {
+ struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+ /* disable the hardware */
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ mutex_destroy(&q->lock);
+
+ if (q->ahb_addr)
+ iounmap(q->ahb_addr);
+
+ return 0;
+}
+
+static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t
+state) {
+ return 0;
+}
+
+static int fsl_qspi_resume(struct platform_device *pdev) {
+ struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+ fsl_qspi_default_setup(q);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_qspi_dt_ids[] = {
+ { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
+ { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
+ { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
+ { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
+ { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
+ { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
+
+static struct platform_driver fsl_qspi_driver = {
+ .driver = {
+ .name = "fsl-quadspi",
+ .of_match_table = fsl_qspi_dt_ids,
+ },
+ .probe = fsl_qspi_probe,
+ .remove = fsl_qspi_remove,
+ .suspend = fsl_qspi_suspend,
+ .resume = fsl_qspi_resume,
+};
+module_platform_driver(fsl_qspi_driver);
+
+MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
+MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_AUTHOR("Boris
+Brezillion <***@bootlin.com>"); MODULE_AUTHOR("Frieder
+Schrempf <***@exceet.de>"); MODULE_LICENSE("GPL v2");
--
2.7.4

Also we should add more debug print messages under dev_dbg() like in func like fsl_qspi_prepare_lut() etc.
Boris Brezillon
2018-06-08 12:51:30 UTC
Permalink
Hi Yogesh,

On Fri, 8 Jun 2018 11:54:12 +0000
Post by Yogesh Narayan Gaur
Hi Frieder,
I have tried to validate your patch on fsl,ls2080a target having 2 Spansion NOR flash, S25FS512S, as slave device.
In Linux boot logs after driver probing is successful, getting below log messages
[ 1.435986] m25p80 spi0.0: found s25fl512s, expected m25p80
[ 1.441564] m25p80 spi0.0: s25fl512s (65536 Kbytes)
[ 1.446972] m25p80 spi0.1: found s25fl512s, expected m25p80
[ 1.452548] m25p80 spi0.1: s25fl512s (65536 Kbytes)
IMHO, we need to correct message as 'found s25fl512s, expected m25p80' as final underlying connected flash device is s25fl512s.
Not sure what you mean here. What would you like us to fix exactly?
Post by Yogesh Narayan Gaur
I have observed data sanity issue after performing read/write operations using MTD interface. Explained below
root:~# mtd_debug erase /dev/mtd0 0x1000000 0x40000
Erased 262144 bytes from address 0x01000000 in flash --> Erase at address 0x1000000 of erase size 0x40000
root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
Copied 256 bytes from address 0x00000000 in flash to rp --> Read 0x100 bytes from flash from address 0x0 in file rp
root:~# mtd_debug write /dev/mtd0 0x1000000 0x100 rp
Copied 256 bytes from rp to address 0x01000000 in flash --> Write 0x100 bytes to flash address 0x1000000 from file rp
root:~# mtd_debug read /dev/mtd0 0x1000000 0x100 wp
Copied 256 bytes from address 0x01000000 in flash to wp --> Read 0x100 bytes from flash from address 0x1000000 in file wp
root:~# diff rp wp --> compare both rp and wp files, if they are different output comes on console stating file are different
Files rp and wp differ
root:~# hexdump wp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 ffff ffff ffff ffff ffff ffff ffff ffff
*
0000100
root:~# hexdump rp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 2403 0000 0000 0000 0000 0000 0000 0000
0000050 0000 0000 0000 0000 0000 0000 0000 0000
*
0000070 0011 0000 09e7 0000 0000 4411 9555 0050
0000080 0000 0000 0000 0000 f9bc afa1 0404 31e0
0000090 0000 0000 0400 31e0 0000 2010 08dc 31eb
00000a0 2880 0050 1300 31eb 4e20 8010 0000 80ff
00000b0 0000 0000 beef dead beef dead beef dead
00000c0 beef dead beef dead beef dead beef dead
*
0000100
root:~#
In hexdump output of the file which being read from address 0x1000000,wp, it can be observed that only first 64 bytes (0x40) are written on the flash.
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0000: 0x2886 instead
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0008: 0xb10f instead
If I remove this patch series and check with older implementation, JFFS2 mounting is working fine.
Problems 2 and 3 should definitely be fixed. That's weird because I
remember that Frieder tested the new driver with a NOR chip, maybe not
with JFFS2 though.
Post by Yogesh Narayan Gaur
With previous driver, we can read content of flash directly using devmem command
Like devmem 0x20000000 "Flash is connected at this Quad-SPI address"
But with new driver devmem interface reporting in-correct value.
This one is clearly not something we should fix. What you were doing is
unsafe (accessing the direct mapping from userspace without making sure
you're the only one to access the device), and making it even more
broken is IMO a better thing. You want to access the memory from
user-space, just use the standard MTD interface (/dev/mtdX).

[...]
Post by Yogesh Narayan Gaur
+
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ u32 lutval[4] = {};
+ int lutidx = 1, i;
+
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+
+ /*
+ * For some unknown reason, using LUT_ADDR doesn't work in some
+ * cases (at least with only one byte long addresses), so
+ * let's use LUT_MODE to write the address bytes one by one
+ */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+ LUT_PAD(op->addr.buswidth),
+ addrbyte);
+ lutidx++;
+ }
+
For ADDR filling in LUT we should use LUT_ADDR only, needs to find out the reason for the issue and we shouldn't use LUT_MODE here.
Just try with a 16-bit address and you'll see it does not work. I don't
know why, and it's more something you should ask to someone working at
NXP ;-).
Post by Yogesh Narayan Gaur
I have few more comments regarding same, mentioned below.
+ if (op->dummy.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ LUT_PAD(op->dummy.buswidth),
+ op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ lutidx++;
+ }
+
+ if (op->data.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ LUT_FSL_READ : LUT_FSL_WRITE,
+ LUT_PAD(op->data.buswidth),
+ 0);
+ lutidx++;
+ }
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+ /* unlock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+
+ /* fill LUT */
+ for (i = 0; i < ARRAY_SIZE(lutval); i++)
+ qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
+
+ /* lock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
+
[...]
Post by Yogesh Narayan Gaur
+static int fsl_qspi_exec_op(struct spi_mem *mem, const struct
+spi_mem_op *op) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ mutex_lock(&q->lock);
+
+ /* wait for the controller being ready */
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
+
+ fsl_qspi_select_mem(q, mem->spi);
+
+ qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);
SFAR should have the actual address where we are doing operation.
Not with the new approach. SFAR is now automatically reconfigured at
each access, and it works because we're not using a LUT_ADDR
instruction but a LUT_MODE one. Sure, I'd prefer to go for the clean
solution with a LUT_ADDR and the address passed through SFAR (+AHB
offset), but it does not work with anything that is not 24 bits or
32 bits wide, which means it does not work when you need to access a SPI
NAND device (on which some addresses are 16 bits wide).
Post by Yogesh Narayan Gaur
For e.g. If reading from flash-0 offset 0x100000 than SFAR should have address as 0x20100000.
As for 'read/write' request 'from/to' respectively been saved in struct spi_mem_op [op.val] this should be added to q->memmap_phy.
You're still thinking as if the driver was only controlling a NOR
device which can be directly addressed. This is not the case for NAND
devices where you first have to load the data in the NAND internal cache
and then read data from the cache.
Post by Yogesh Narayan Gaur
In LUT preparation for ADDR, we should use ADDR_WIDTH as 3-byte or 4-byte addressing only.
Please have a look at SPI NAND datasheets and you'll see it's simply
not possible. So, either NXP doesn't want his QSPI controller to
interface with anything except NORs or we have to use the trick we have
here (LUT_MODE instead of LUT_ADDR).
Post by Yogesh Narayan Gaur
Start address should be saved in SFAR register.
+
+ qspi_writel(q,
+ qspi_readl(q, base + QUADSPI_MCR) |
+ QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+ base + QUADSPI_MCR);
+
+ qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+ base + QUADSPI_SPTRCLR);
+
+ fsl_qspi_prepare_lut(q, op);
+
+ /*
+ * If we have large chunks of data, we read them through the AHB bus
+ * by accessing the mapped memory. In all other cases we use
+ * IP commands to access the flash.
+ */
+ if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+ op->data.dir == SPI_MEM_DATA_IN) {
+ fsl_qspi_read_ahb(q, op);
+ } else {
+ qspi_writel(q,
+ QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+ fsl_qspi_fill_txfifo(q, op);
+
+ err = fsl_qspi_do_op(q, op);
+ }
+
+ mutex_unlock(&q->lock);
+
+ return err;
+}
[...]
Post by Yogesh Narayan Gaur
Also we should add more debug print messages under dev_dbg() like in func like fsl_qspi_prepare_lut() etc.
Would you mind giving more details about where you'd like this traces
to be placed exactly and what information you'd like to display?

Thanks,

Boris
Yogesh Narayan Gaur
2018-06-11 06:31:00 UTC
Permalink
Hi Boris,


-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Friday, June 8, 2018 6:22 PM
To: Yogesh Narayan Gaur <***@nxp.com>
Cc: Frieder Schrempf <***@exceet.de>; linux-***@lists.infradead.org; linux-***@vger.kernel.org; ***@infradead.org; ***@gmail.com; ***@gmail.com; ***@nod.at; ***@bootlin.com; ***@kernel.org; David Wolfe <***@nxp.com>; Fabio Estevam <***@nxp.com>; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

Hi Yogesh,

On Fri, 8 Jun 2018 11:54:12 +0000
Post by Yogesh Narayan Gaur
Hi Frieder,
I have tried to validate your patch on fsl,ls2080a target having 2 Spansion NOR flash, S25FS512S, as slave device.
In Linux boot logs after driver probing is successful, getting below log messages
[ 1.435986] m25p80 spi0.0: found s25fl512s, expected m25p80
[ 1.441564] m25p80 spi0.0: s25fl512s (65536 Kbytes)
[ 1.446972] m25p80 spi0.1: found s25fl512s, expected m25p80
[ 1.452548] m25p80 spi0.1: s25fl512s (65536 Kbytes)
IMHO, we need to correct message as 'found s25fl512s, expected m25p80' as final underlying connected flash device is s25fl512s.
Not sure what you mean here. What would you like us to fix exactly?
Post by Yogesh Narayan Gaur
I have observed data sanity issue after performing read/write
operations using MTD interface. Explained below
root:~# mtd_debug erase /dev/mtd0 0x1000000 0x40000
Erased 262144 bytes from address 0x01000000 in flash --> Erase at address 0x1000000 of erase size 0x40000
root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
Copied 256 bytes from address 0x00000000 in flash to rp --> Read 0x100 bytes from flash from address 0x0 in file rp
root:~# mtd_debug write /dev/mtd0 0x1000000 0x100 rp
Copied 256 bytes from rp to address 0x01000000 in flash --> Write 0x100 bytes to flash address 0x1000000 from file rp
root:~# mtd_debug read /dev/mtd0 0x1000000 0x100 wp
Copied 256 bytes from address 0x01000000 in flash to wp --> Read 0x100 bytes from flash from address 0x1000000 in file wp
root:~# diff rp wp --> compare both rp and wp files, if they are different output comes on console stating file are different
Files rp and wp differ
root:~# hexdump wp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 ffff ffff ffff ffff ffff ffff ffff ffff
*
0000100
root:~# hexdump rp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 2403 0000 0000 0000 0000 0000 0000 0000
0000050 0000 0000 0000 0000 0000 0000 0000 0000
*
0000070 0011 0000 09e7 0000 0000 4411 9555 0050
0000080 0000 0000 0000 0000 f9bc afa1 0404 31e0
0000090 0000 0000 0400 31e0 0000 2010 08dc 31eb
00000a0 2880 0050 1300 31eb 4e20 8010 0000 80ff
00000b0 0000 0000 beef dead beef dead beef dead
00000c0 beef dead beef dead beef dead beef dead
*
0000100
root:~#
In hexdump output of the file which being read from address 0x1000000,wp, it can be observed that only first 64 bytes (0x40) are written on the flash.
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0000: 0x2886 instead
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0008: 0xb10f instead
If I remove this patch series and check with older implementation, JFFS2 mounting is working fine.
Problems 2 and 3 should definitely be fixed. That's weird because I remember that Frieder tested the new driver with a NOR chip, maybe not with JFFS2 though.

For write issue, it would be happening due to the changes pushed in spi-mem framework.

I have added my comment in that patch[1].

[1] https://patchwork.ozlabs.org/patch/869629/
Post by Yogesh Narayan Gaur
With previous driver, we can read content of flash directly using
devmem command Like devmem 0x20000000 "Flash is connected at this Quad-SPI address"
But with new driver devmem interface reporting in-correct value.
This one is clearly not something we should fix. What you were doing is unsafe (accessing the direct mapping from userspace without making sure you're the only one to access the device), and making it even more broken is IMO a better thing. You want to access the memory from user-space, just use the standard MTD interface (/dev/mtdX).

Let me check how devmem interface is working.

--
Regards
Yogesh Gaur

[...]
Post by Yogesh Narayan Gaur
+
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = q->iobase;
+ u32 lutval[4] = {};
+ int lutidx = 1, i;
+
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+
+ /*
+ * For some unknown reason, using LUT_ADDR doesn't work in some
+ * cases (at least with only one byte long addresses), so
+ * let's use LUT_MODE to write the address bytes one by one
+ */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+ LUT_PAD(op->addr.buswidth),
+ addrbyte);
+ lutidx++;
+ }
+
For ADDR filling in LUT we should use LUT_ADDR only, needs to find out the reason for the issue and we shouldn't use LUT_MODE here.
Just try with a 16-bit address and you'll see it does not work. I don't know why, and it's more something you should ask to someone working at NXP ;-).
Post by Yogesh Narayan Gaur
I have few more comments regarding same, mentioned below.
+ if (op->dummy.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ LUT_PAD(op->dummy.buswidth),
+ op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ lutidx++;
+ }
+
+ if (op->data.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ LUT_FSL_READ : LUT_FSL_WRITE,
+ LUT_PAD(op->data.buswidth),
+ 0);
+ lutidx++;
+ }
+
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+ /* unlock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+
+ /* fill LUT */
+ for (i = 0; i < ARRAY_SIZE(lutval); i++)
+ qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
+
+ /* lock LUT */
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
+
[...]
Post by Yogesh Narayan Gaur
+static int fsl_qspi_exec_op(struct spi_mem *mem, const struct
+spi_mem_op *op) {
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ void __iomem *base = q->iobase;
+ int err = 0;
+
+ mutex_lock(&q->lock);
+
+ /* wait for the controller being ready */
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
+
+ fsl_qspi_select_mem(q, mem->spi);
+
+ qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);
SFAR should have the actual address where we are doing operation.
Not with the new approach. SFAR is now automatically reconfigured at each access, and it works because we're not using a LUT_ADDR instruction but a LUT_MODE one. Sure, I'd prefer to go for the clean solution with a LUT_ADDR and the address passed through SFAR (+AHB offset), but it does not work with anything that is not 24 bits or
32 bits wide, which means it does not work when you need to access a SPI NAND device (on which some addresses are 16 bits wide).
Post by Yogesh Narayan Gaur
For e.g. If reading from flash-0 offset 0x100000 than SFAR should have address as 0x20100000.
As for 'read/write' request 'from/to' respectively been saved in struct spi_mem_op [op.val] this should be added to q->memmap_phy.
You're still thinking as if the driver was only controlling a NOR device which can be directly addressed. This is not the case for NAND devices where you first have to load the data in the NAND internal cache and then read data from the cache.
Post by Yogesh Narayan Gaur
In LUT preparation for ADDR, we should use ADDR_WIDTH as 3-byte or 4-byte addressing only.
Please have a look at SPI NAND datasheets and you'll see it's simply not possible. So, either NXP doesn't want his QSPI controller to interface with anything except NORs or we have to use the trick we have here (LUT_MODE instead of LUT_ADDR).
Post by Yogesh Narayan Gaur
Start address should be saved in SFAR register.
+
+ qspi_writel(q,
+ qspi_readl(q, base + QUADSPI_MCR) |
+ QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+ base + QUADSPI_MCR);
+
+ qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+ base + QUADSPI_SPTRCLR);
+
+ fsl_qspi_prepare_lut(q, op);
+
+ /*
+ * If we have large chunks of data, we read them through the AHB bus
+ * by accessing the mapped memory. In all other cases we use
+ * IP commands to access the flash.
+ */
+ if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+ op->data.dir == SPI_MEM_DATA_IN) {
+ fsl_qspi_read_ahb(q, op);
+ } else {
+ qspi_writel(q,
+ QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+ fsl_qspi_fill_txfifo(q, op);
+
+ err = fsl_qspi_do_op(q, op);
+ }
+
+ mutex_unlock(&q->lock);
+
+ return err;
+}
[...]
Post by Yogesh Narayan Gaur
Also we should add more debug print messages under dev_dbg() like in func like fsl_qspi_prepare_lut() etc.
Would you mind giving more details about where you'd like this traces to be placed exactly and what information you'd like to display?

Thanks,

Boris
Boris Brezillon
2018-06-11 07:46:16 UTC
Permalink
Hi Yogesh,

On Mon, 11 Jun 2018 06:31:00 +0000
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
I have observed data sanity issue after performing read/write
operations using MTD interface. Explained below
root:~# mtd_debug erase /dev/mtd0 0x1000000 0x40000
Erased 262144 bytes from address 0x01000000 in flash --> Erase at address 0x1000000 of erase size 0x40000
root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
Copied 256 bytes from address 0x00000000 in flash to rp --> Read 0x100 bytes from flash from address 0x0 in file rp
root:~# mtd_debug write /dev/mtd0 0x1000000 0x100 rp
Copied 256 bytes from rp to address 0x01000000 in flash --> Write 0x100 bytes to flash address 0x1000000 from file rp
root:~# mtd_debug read /dev/mtd0 0x1000000 0x100 wp
Copied 256 bytes from address 0x01000000 in flash to wp --> Read 0x100 bytes from flash from address 0x1000000 in file wp
root:~# diff rp wp --> compare both rp and wp files, if they are different output comes on console stating file are different
Files rp and wp differ
root:~# hexdump wp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 ffff ffff ffff ffff ffff ffff ffff ffff
*
0000100
root:~# hexdump rp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 2403 0000 0000 0000 0000 0000 0000 0000
0000050 0000 0000 0000 0000 0000 0000 0000 0000
*
0000070 0011 0000 09e7 0000 0000 4411 9555 0050
0000080 0000 0000 0000 0000 f9bc afa1 0404 31e0
0000090 0000 0000 0400 31e0 0000 2010 08dc 31eb
00000a0 2880 0050 1300 31eb 4e20 8010 0000 80ff
00000b0 0000 0000 beef dead beef dead beef dead
00000c0 beef dead beef dead beef dead beef dead
*
0000100
root:~#
In hexdump output of the file which being read from address 0x1000000,wp, it can be observed that only first 64 bytes (0x40) are written on the flash.
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0000: 0x2886 instead
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0008: 0xb10f instead
If I remove this patch series and check with older implementation, JFFS2 mounting is working fine.
Problems 2 and 3 should definitely be fixed. That's weird because I remember that Frieder tested the new driver with a NOR chip, maybe not with JFFS2 though.
For write issue, it would be happening due to the changes pushed in spi-mem framework.
Now I understand why Frieder didn't face this issue: he was testing on
an imx6 which has a 512 bytes TX FIFO, while you're probably testing on
a vhybrid or layerscape platform which only has a 64 bytes TX FIFO.

I think it's time to accept having partial page writes. This has come
up several times (last time was [1]) and it looks like the fsl quadspi
driver was already doing this sort of things (well hidden in the probe
path [2] :-)).

Marek, any comment on that?

Regards,

Boris

[1]https://patchwork.ozlabs.org/patch/905507/
[2]https://elixir.bootlin.com/linux/v4.17/source/drivers/mtd/spi-nor/fsl-quadspi.c#L1106
Yogesh Narayan Gaur
2018-06-11 09:38:14 UTC
Permalink
Hi Boris,

-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Monday, June 11, 2018 1:16 PM
To: Yogesh Narayan Gaur <***@nxp.com>; ***@gmail.com
Cc: Frieder Schrempf <***@exceet.de>; linux-***@lists.infradead.org; linux-***@vger.kernel.org; ***@infradead.org; ***@gmail.com; ***@nod.at; ***@bootlin.com; ***@kernel.org; David Wolfe <***@nxp.com>; Fabio Estevam <***@nxp.com>; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

Hi Yogesh,

On Mon, 11 Jun 2018 06:31:00 +0000
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
I have observed data sanity issue after performing read/write
operations using MTD interface. Explained below
root:~# mtd_debug erase /dev/mtd0 0x1000000 0x40000
Erased 262144 bytes from address 0x01000000 in flash --> Erase at address 0x1000000 of erase size 0x40000
root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
Copied 256 bytes from address 0x00000000 in flash to rp --> Read 0x100 bytes from flash from address 0x0 in file rp
root:~# mtd_debug write /dev/mtd0 0x1000000 0x100 rp
Copied 256 bytes from rp to address 0x01000000 in flash --> Write 0x100 bytes to flash address 0x1000000 from file rp
root:~# mtd_debug read /dev/mtd0 0x1000000 0x100 wp
Copied 256 bytes from address 0x01000000 in flash to wp --> Read 0x100 bytes from flash from address 0x1000000 in file wp
root:~# diff rp wp --> compare both rp and wp files, if they are different output comes on console stating file are different
Files rp and wp differ
root:~# hexdump wp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 ffff ffff ffff ffff ffff ffff ffff ffff
*
0000100
root:~# hexdump rp
0000000 aa55 aa55 0000 8010 541c 4000 0040 0000
0000010 0000 0000 0000 0000 0000 0000 0000 000a
0000020 0000 0030 0000 0000 11a0 00a0 2580 0000
0000030 0000 0000 0040 0000 005b 0000 0000 0000
0000040 2403 0000 0000 0000 0000 0000 0000 0000
0000050 0000 0000 0000 0000 0000 0000 0000 0000
*
0000070 0011 0000 09e7 0000 0000 4411 9555 0050
0000080 0000 0000 0000 0000 f9bc afa1 0404 31e0
0000090 0000 0000 0400 31e0 0000 2010 08dc 31eb
00000a0 2880 0050 1300 31eb 4e20 8010 0000 80ff
00000b0 0000 0000 beef dead beef dead beef dead
00000c0 beef dead beef dead beef dead beef dead
*
0000100
root:~#
In hexdump output of the file which being read from address 0x1000000,wp, it can be observed that only first 64 bytes (0x40) are written on the flash.
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0000: 0x2886 instead
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0008: 0xb10f instead
If I remove this patch series and check with older implementation, JFFS2 mounting is working fine.
Problems 2 and 3 should definitely be fixed. That's weird because I remember that Frieder tested the new driver with a NOR chip, maybe not with JFFS2 though.
For write issue, it would be happening due to the changes pushed in spi-mem framework.
Now I understand why Frieder didn't face this issue: he was testing on an imx6 which has a 512 bytes TX FIFO, while you're probably testing on a vhybrid or layerscape platform which only has a 64 bytes TX FIFO.

I think it's time to accept having partial page writes. This has come up several times (last time was [1]) and it looks like the fsl quadspi driver was already doing this sort of things (well hidden in the probe path [2] :-)).

Marek, any comment on that?

Regards,

Boris

[1]https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F905507%2F&data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C6f2e208553754619956f08d5cf6f71f6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636642999952927107&sdata=GrexQ%2FjjJVU282cKr4CuVnYg5NvBL9ZZDFeIcBSBB6k%3D&reserved=0
[2]https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv4.17%2Fsource%2Fdrivers%2Fmtd%2Fspi-nor%2Ffsl-quadspi.c%23L1106&data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C6f2e208553754619956f08d5cf6f71f6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636642999952927107&sdata=kIrwvaYA4RrhghhNx6iXsGcEE2j2KY%2BhMJdRRIuu8vo%3D&reserved=0

I have send the patch[1] based on shared patch for review, this patch is based on the git[2]
With this change, my write is start working for data size requested bigger than TX FIFO size but JFFS2 mounting is still failing.

--
Regards
Yogesh Gaur.

[1] https://patchwork.ozlabs.org/patch/927587/
[2] https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-4.18
Boris Brezillon
2018-06-11 10:16:18 UTC
Permalink
On Mon, 11 Jun 2018 09:38:14 +0000
Post by Yogesh Narayan Gaur
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
When I do mtd1 + mtd2 + mtd3, I end up with 0x3d00000 instead of
0x4000000. Is that normal? Do you reserve a bit of space at the end or
is it that rcw is not starting at 0?
Post by Yogesh Narayan Gaur
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0000: 0x2886 instead
Did you try to create a smaller partition? Maybe we have a problem when
accessing addresses higher than X with the new driver (X to be
determined).
Post by Yogesh Narayan Gaur
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0008: 0xb10f instead
Yogesh Narayan Gaur
2018-06-11 10:21:22 UTC
Permalink
Hi Boris,

-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Monday, June 11, 2018 3:46 PM
To: Yogesh Narayan Gaur <***@nxp.com>
Cc: ***@gmail.com; Frieder Schrempf <***@exceet.de>; linux-***@lists.infradead.org; linux-***@vger.kernel.org; ***@infradead.org; ***@gmail.com; ***@nod.at; ***@bootlin.com; ***@kernel.org; David Wolfe <***@nxp.com>; Fabio Estevam <***@nxp.com>; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

On Mon, 11 Jun 2018 09:38:14 +0000
Post by Yogesh Narayan Gaur
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
When I do mtd1 + mtd2 + mtd3, I end up with 0x3d00000 instead of 0x4000000. Is that normal? Do you reserve a bit of space at the end or is it that rcw is not starting at 0?

I have given partition size n bootargs as mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs)
5 + 10 + 46 ==> 61M i.e. 0x3d00000.
I have just reserve the bit at the end, we can modify these settings also.
Post by Yogesh Narayan Gaur
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0000: 0x2886 instead
Did you try to create a smaller partition? Maybe we have a problem when accessing addresses higher than X with the new driver (X to be determined).

Would try and update you.

--
Regards
Yogesh Gaur
Post by Yogesh Narayan Gaur
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0008: 0xb10f instead
Yogesh Narayan Gaur
2018-06-12 06:42:42 UTC
Permalink
Hi Boris,

-----Original Message-----
From: linux-mtd [mailto:linux-mtd-***@lists.infradead.org] On Behalf Of Yogesh Narayan Gaur
Sent: Monday, June 11, 2018 3:51 PM
To: Boris Brezillon <***@bootlin.com>
Cc: ***@nod.at; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org; linux-***@vger.kernel.org; ***@gmail.com; Frieder Schrempf <***@exceet.de>; ***@kernel.org; linux-***@lists.infradead.org; ***@bootlin.com; Fabio Estevam <***@nxp.com>; David Wolfe <***@nxp.com>; ***@gmail.com; ***@infradead.org
Subject: RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

Hi Boris,

-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Monday, June 11, 2018 3:46 PM
To: Yogesh Narayan Gaur <***@nxp.com>
Cc: ***@gmail.com; Frieder Schrempf <***@exceet.de>; linux-***@lists.infradead.org; linux-***@vger.kernel.org; ***@infradead.org; ***@gmail.com; ***@nod.at; ***@bootlin.com; ***@kernel.org; David Wolfe <***@nxp.com>; Fabio Estevam <***@nxp.com>; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

On Mon, 11 Jun 2018 09:38:14 +0000
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 commands should work fine on NOR flash.
But with this driver change my mount command is not working.
In my target there are 2 flash slave devices connected, and I have given argument to create MTD partition like "mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
Below is output for /proc/mtd commands
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0" --> First 64MB flash
mtd1: 00500000 00040000 "rcw" --> Second 64 MB flash device, 3 MTD partition are created for it.
mtd2: 00a00000 00040000 "test"
mtd3: 02e00000 00040000 "rootfs"
When I do mtd1 + mtd2 + mtd3, I end up with 0x3d00000 instead of 0x4000000. Is that normal? Do you reserve a bit of space at the end or is it that rcw is not starting at 0?

I have given partition size n bootargs as mtdparts=20c0000.quadspi-1:5M(rcw),10M(test),46M(rootfs)
5 + 10 + 46 ==> 61M i.e. 0x3d00000.
I have just reserve the bit at the end, we can modify these settings also.
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
This command didn't finish successfully and there are lot of messages coming on console mentioning failure in jffs2_scan_eraseblock()
[ 187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0000: 0x2886 instead
Did you try to create a smaller partition? Maybe we have a problem when accessing addresses higher than X with the new driver (X to be determined).
Would try and update you.
I have tried JFFS2 mounting with smaller partition size but still getting failure.
For partition size equal or less than 1MB, getting errors as
[ 25.044930] jffs2: Too few erase blocks (4)
Thus, need to have size more than 1MB.

For 2MB partition size getting error message from jffs2_scan_eraseblock().
***@ls1012ardb:~# cat /proc/mtd
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0"
mtd1: 00500000 00040000 "rcw"
mtd2: 00a00000 00040000 "test"
mtd3: 00200000 00040000 "rootfs"
***@ls1012ardb:~# mkdir /media/ram ; flash_eraseall /dev/mtd3
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
Erasing 256 Kibyte @ 1c0000 -- 100 % complete
***@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/
[ 26.380989] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000000: 0x0dd0 instead
[ 26.390509] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000004c: 0x7366 instead
[ 26.399999] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000050: 0x736c instead

--
Regards
Yogesh Gaur
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
Post by Yogesh Narayan Gaur
[ 187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x013c0004: 0x7a3b instead
[ 187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
0x1985 not found at 0x013c0008: 0xb10f instead
______________________________________________________
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Boris Brezillon
2018-06-12 07:13:28 UTC
Permalink
On Tue, 12 Jun 2018 06:42:42 +0000
Post by Yogesh Narayan Gaur
I have tried JFFS2 mounting with smaller partition size but still getting failure.
For partition size equal or less than 1MB, getting errors as
[ 25.044930] jffs2: Too few erase blocks (4)
Thus, need to have size more than 1MB.
For 2MB partition size getting error message from jffs2_scan_eraseblock().
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0"
mtd1: 00500000 00040000 "rcw"
mtd2: 00a00000 00040000 "test"
mtd3: 00200000 00040000 "rootfs"
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
[ 26.380989] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000000: 0x0dd0 instead
[ 26.390509] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000004c: 0x7366 instead
[ 26.399999] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000050: 0x736c instead
That's weird. Can you tell me on which platform you're testing?
lsxxx or vf610? Can you dump the NOR after the erase to make sure the
memory is actually erased (filled with 0xff)?
Yogesh Narayan Gaur
2018-06-12 08:51:25 UTC
Permalink
Hi Boris,

-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Tuesday, June 12, 2018 12:43 PM
To: Yogesh Narayan Gaur <***@nxp.com>
Cc: ***@nod.at; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org; linux-***@vger.kernel.org; ***@gmail.com; Frieder Schrempf <***@exceet.de>; ***@kernel.org; linux-***@lists.infradead.org; ***@bootlin.com; Fabio Estevam <***@nxp.com>; David Wolfe <***@nxp.com>; ***@gmail.com; ***@infradead.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

On Tue, 12 Jun 2018 06:42:42 +0000
Post by Yogesh Narayan Gaur
I have tried JFFS2 mounting with smaller partition size but still getting failure.
For partition size equal or less than 1MB, getting errors as
[ 25.044930] jffs2: Too few erase blocks (4)
Thus, need to have size more than 1MB.
For 2MB partition size getting error message from jffs2_scan_eraseblock().
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0"
mtd1: 00500000 00040000 "rcw"
mtd2: 00a00000 00040000 "test"
mtd3: 00200000 00040000 "rootfs"
flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it
[ 26.380989] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000000: 0x0dd0 instead
[ 26.390509] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000004c: 0x7366 instead
[ 26.399999] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000050: 0x736c instead
That's weird. Can you tell me on which platform you're testing?
lsxxx or vf610? Can you dump the NOR after the erase to make sure the memory is actually erased (filled with 0xff)?

I am working on lsxxx platform. With further debugging, I found that my erase operation for second flash device is not working properly.
Need to have debugging for this in Frieder Patch.

When I have created multiple partition for First flash device, then JFFS2 mounting and booting of Linux kernel from rootfstype=jffs2 is successful.
***@ls1012ardb:~# cat /proc/mtd
dev: size erasesize name
mtd0: 00500000 00040000 "rcw"
mtd1: 00a00000 00040000 "test"
mtd2: 02e00000 00040000 "rootfs"
mtd3: 04000000 00040000 "20c0000.quadspi-1"
In above list, for MTD2 partition, able to perform JFFS2 mounting.

Below is logs of erase for both flashes:
***@ls1012ardb:~# cat /proc/mtd
dev: size erasesize name
mtd0: 04000000 00040000 "20c0000.quadspi-0"
mtd1: 04000000 00040000 "20c0000.quadspi-1"
***@ls1012ardb:~# mtd_debug erase /dev/mtd0 0x1000000 0x2000000
Erased 33554432 bytes from address 0x01000000 in flash
***@ls1012ardb:~#
***@ls1012ardb:~# mtd_debug read /dev/mtd0 0x1000000 0xa00000 rp
Copied 10485760 bytes from address 0x01000000 in flash to rp
***@ls1012ardb:~# hexdump rp
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0a00000
***@ls1012ardb:~#
***@ls1012ardb:~# mtd_debug erase /dev/mtd1 0x1000000 0x2000000
[ 25.023027] random: crng init done
Erased 33554432 bytes from address 0x01000000 in flash
***@ls1012ardb:~# mtd_debug read /dev/mtd1 0x1000000 0xa00000 rp
Copied 10485760 bytes from address 0x01000000 in flash to rp
***@ls1012ardb:~#
***@ls1012ardb:~# hexdump rp
0000000 1985 2003 000c 0000 b0b1 e41e ffff ffff
0000010 ffff ffff ffff ffff ffff ffff ffff ffff
*
0040000 1985 2003 000c 0000 b0b1 e41e ffff ffff
0040010 ffff ffff ffff ffff ffff ffff ffff ffff

--
Yogesh Gaur
Boris Brezillon
2018-06-15 12:50:19 UTC
Permalink
On Tue, 12 Jun 2018 08:51:25 +0000
Post by Yogesh Narayan Gaur
I am working on lsxxx platform. With further debugging, I found that my erase operation for second flash device is not working properly.
Need to have debugging for this in Frieder Patch.
Did you find the problem? Could it be a wrong "reg = <>" definition in
your DT (Frieder changed the CS numbering scheme in the new driver)?
Yogesh Narayan Gaur
2018-06-15 13:42:12 UTC
Permalink
Hi Boris,

I am still debugging the issue.
With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.

In current code, value of map_addr are being assigned to these register.
map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;

qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));

But instead of "q->devtype_data->ahb_buf_size" it should be flash size.
For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);

Thus, there should be mechanism or the entry in structure where we can have the information of the size of the connected slave device.

With both of above hardcoded changes, I am able to perform Write and Erase operation on my second flash device but still facing issue in Read operation, debugging in progress for that.

--
Regards
Yogesh Gaur


-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Friday, June 15, 2018 6:20 PM
To: Yogesh Narayan Gaur <***@nxp.com>
Cc: ***@nod.at; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org; linux-***@vger.kernel.org; ***@gmail.com; Frieder Schrempf <***@exceet.de>; ***@kernel.org; linux-***@lists.infradead.org; ***@bootlin.com; Fabio Estevam <***@nxp.com>; David Wolfe <***@nxp.com>; ***@gmail.com; ***@infradead.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

On Tue, 12 Jun 2018 08:51:25 +0000
Post by Yogesh Narayan Gaur
I am working on lsxxx platform. With further debugging, I found that my erase operation for second flash device is not working properly.
Need to have debugging for this in Frieder Patch.
Did you find the problem? Could it be a wrong "reg = <>" definition in your DT (Frieder changed the CS numbering scheme in the new driver)?
Boris Brezillon
2018-06-15 13:55:41 UTC
Permalink
On Fri, 15 Jun 2018 13:42:12 +0000
Post by Frieder Schrempf
Hi Boris,
I am still debugging the issue.
With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
In current code, value of map_addr are being assigned to these register.
map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;
qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
But instead of "q->devtype_data->ahb_buf_size" it should be flash size.
No, because we're only using 2 * ->ahb_buf_size in the direct mapping
for each device, and we're modifying the mapping dynamically based on
the selected device. Maybe we got the logic wrong though.
Post by Frieder Schrempf
For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);
I don't want to expose the full device in the direct mapping yet
(that's part of the direct-mapping API I posted here [1]). What this
version of the driver does is, map only 2 time the ahb_size so that we
can bypass the internal cache of the QSPI engine.
Post by Frieder Schrempf
Thus, there should be mechanism or the entry in structure where we can have the information of the size of the connected slave device.
Because that's exactly the kind of thing I'd like to avoid. What if the
device is bigger than the reserved memory region? What if the sum of
all devices does not fit in there? Here I tried to support all cases by
just mapping the portion of memory we need.
Boris Brezillon
2018-06-15 13:58:23 UTC
Permalink
On Fri, 15 Jun 2018 15:55:41 +0200
Post by Boris Brezillon
On Fri, 15 Jun 2018 13:42:12 +0000
Post by Frieder Schrempf
Hi Boris,
I am still debugging the issue.
With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
In current code, value of map_addr are being assigned to these register.
map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;
qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
But instead of "q->devtype_data->ahb_buf_size" it should be flash size.
No, because we're only using 2 * ->ahb_buf_size in the direct mapping
for each device, and we're modifying the mapping dynamically based on
the selected device. Maybe we got the logic wrong though.
Post by Frieder Schrempf
For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);
I don't want to expose the full device in the direct mapping yet
(that's part of the direct-mapping API I posted here [1]). What this
version of the driver does is, map only 2 time the ahb_size so that we
can bypass the internal cache of the QSPI engine.
Oops, forgot to add the link.

[1]http://lists.infradead.org/pipermail/linux-mtd/2018-June/081460.html
Yogesh Narayan Gaur
2018-06-18 13:32:27 UTC
Permalink
-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Friday, June 15, 2018 7:26 PM
To: Yogesh Narayan Gaur <***@nxp.com>; Fabio Estevam <***@nxp.com>; David Wolfe <***@nxp.com>; ***@infradead.org
Cc: ***@nod.at; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org; linux-***@vger.kernel.org; ***@gmail.com; Frieder Schrempf <***@exceet.de>; ***@kernel.org; linux-***@lists.infradead.org; ***@bootlin.com; ***@gmail.com
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

On Fri, 15 Jun 2018 13:42:12 +0000
Post by Frieder Schrempf
Hi Boris,
I am still debugging the issue.
With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
In current code, value of map_addr are being assigned to these register.
map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;
qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
But instead of "q->devtype_data->ahb_buf_size" it should be flash size.
No, because we're only using 2 * ->ahb_buf_size in the direct mapping for each device, and we're modifying the mapping dynamically based on the selected device. Maybe we got the logic wrong though.

Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need to save starting actual address from where this flash is getting started.
Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD would have value of q->memmap_phy + 0x4000000 i.e. (QUADSPI_SFA1AD + sizeof First Flash)
If second flash is of size 32MB, then register QUADSPI_SFB1AD would have value of value of QUADSPI_SFA2AD + sizeof second flash.
Post by Frieder Schrempf
For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);
I don't want to expose the full device in the direct mapping yet (that's part of the direct-mapping API I posted here [1]). What this version of the driver does is, map only 2 time the ahb_size so that we can bypass the internal cache of the QSPI engine.

To perform any operation on second flash, we need to provide it's base address should be saved in SFAR register for this particular operation.
Exposing only 2 time of ahb_size is design decision but value in SFAR register should be correct.
Post by Frieder Schrempf
Thus, there should be mechanism or the entry in structure where we can have the information of the size of the connected slave device.
Because that's exactly the kind of thing I'd like to avoid. What if the device is bigger than the reserved memory region? What if the sum of all devices does not fit in there? Here I tried to support all cases by just mapping the portion of memory we need.

So IMO, there should be mechanism to have value of start address of each slave device. This might can be done from DTS entry of each slave device connected to the controller.
Boris Brezillon
2018-06-18 19:15:36 UTC
Permalink
Hi Yogesh,

On Mon, 18 Jun 2018 13:32:27 +0000
Post by Yogesh Narayan Gaur
-----Original Message-----
Sent: Friday, June 15, 2018 7:26 PM
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller
On Fri, 15 Jun 2018 13:42:12 +0000
Post by Frieder Schrempf
Hi Boris,
I am still debugging the issue.
With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
In current code, value of map_addr are being assigned to these register.
map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;
qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
But instead of "q->devtype_data->ahb_buf_size" it should be flash size.
No, because we're only using 2 * ->ahb_buf_size in the direct mapping for each device, and we're modifying the mapping dynamically based on the selected device. Maybe we got the logic wrong though.
Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need to save starting actual address from where this flash is getting started.
Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD would have value of q->memmap_phy + 0x4000000 i.e. (QUADSPI_SFA1AD + sizeof First Flash)
If second flash is of size 32MB, then register QUADSPI_SFB1AD would have value of value of QUADSPI_SFA2AD + sizeof second flash.
Again, no, that's not what I'm trying to do, and the fact that it
worked fine with CS0 makes me think you don't need to map the whole
device to get it to work, just 2 * ->ahb_buf_size per device.
Post by Yogesh Narayan Gaur
Post by Frieder Schrempf
For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);
I don't want to expose the full device in the direct mapping yet (that's part of the direct-mapping API I posted here [1]). What this version of the driver does is, map only 2 time the ahb_size so that we can bypass the internal cache of the QSPI engine.
To perform any operation on second flash, we need to provide it's base address should be saved in SFAR register for this particular operation.
That's what we tried to do, we tried to make all CS start at 0 when they
are used and declare unused CS at having a size of 0.

So, say you're trying to access CS1, you should have the following
ranges:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)
CS2: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)
CS3: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)

now, if you're trying to access CS3:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 0 (size = 0)
CS2: 0 -> 0 (size = 0)
CS3: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)

maybe this approach does not work, but that's not clearly stated as
'not supported' in the datasheet.
Post by Yogesh Narayan Gaur
Exposing only 2 time of ahb_size is design decision but value in SFAR register should be correct.
Post by Frieder Schrempf
Thus, there should be mechanism or the entry in structure where we can have the information of the size of the connected slave device.
Because that's exactly the kind of thing I'd like to avoid. What if the device is bigger than the reserved memory region? What if the sum of all devices does not fit in there? Here I tried to support all cases by just mapping the portion of memory we need.
So IMO, there should be mechanism to have value of start address of each slave device. This might can be done from DTS entry of each slave device connected to the controller.
Let's not put that in the DT. If we really can't re-use 0 as the start
address and make some ranges 0 in size, then let's reserve 2 *
->ahb_buf_size per chip, and be done with it.

This should leave us enough space in the AHB mem range to then support
temporary direct mappings through the direct mapping API.

Regards,

Boris
Yogesh Narayan Gaur
2018-06-19 07:10:37 UTC
Permalink
Hi Boris,

-----Original Message-----
From: Boris Brezillon [mailto:***@bootlin.com]
Sent: Tuesday, June 19, 2018 12:46 AM
To: Yogesh Narayan Gaur <***@nxp.com>
Cc: Fabio Estevam <***@nxp.com>; David Wolfe <***@nxp.com>; ***@infradead.org; ***@nod.at; Prabhakar Kushwaha <***@nxp.com>; Han Xu <***@nxp.com>; linux-***@vger.kernel.org; linux-***@vger.kernel.org; ***@gmail.com; Frieder Schrempf <***@exceet.de>; ***@kernel.org; linux-***@lists.infradead.org; ***@bootlin.com; ***@gmail.com
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

Hi Yogesh,

On Mon, 18 Jun 2018 13:32:27 +0000
Post by Yogesh Narayan Gaur
-----Original Message-----
Sent: Friday, June 15, 2018 7:26 PM
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller
On Fri, 15 Jun 2018 13:42:12 +0000
Post by Frieder Schrempf
Hi Boris,
I am still debugging the issue.
With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
In current code, value of map_addr are being assigned to these register.
map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;
qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
But instead of "q->devtype_data->ahb_buf_size" it should be flash size.
No, because we're only using 2 * ->ahb_buf_size in the direct mapping for each device, and we're modifying the mapping dynamically based on the selected device. Maybe we got the logic wrong though.
Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need to save starting actual address from where this flash is getting started.
Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD
would have value of q->memmap_phy + 0x4000000 i.e. (QUADSPI_SFA1AD + sizeof First Flash) If second flash is of size 32MB, then register QUADSPI_SFB1AD would have value of value of QUADSPI_SFA2AD + sizeof second flash.
Again, no, that's not what I'm trying to do, and the fact that it worked fine with CS0 makes me think you don't need to map the whole device to get it to work, just 2 * ->ahb_buf_size per device.
Post by Yogesh Narayan Gaur
Post by Frieder Schrempf
For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);
I don't want to expose the full device in the direct mapping yet (that's part of the direct-mapping API I posted here [1]). What this version of the driver does is, map only 2 time the ahb_size so that we can bypass the internal cache of the QSPI engine.
To perform any operation on second flash, we need to provide it's base address should be saved in SFAR register for this particular operation.
That's what we tried to do, we tried to make all CS start at 0 when they are used and declare unused CS at having a size of 0.

So, say you're trying to access CS1, you should have the following
ranges:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)
CS2: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)
CS3: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)

now, if you're trying to access CS3:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 0 (size = 0)
CS2: 0 -> 0 (size = 0)
CS3: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)

maybe this approach does not work, but that's not clearly stated as 'not supported' in the datasheet.
Post by Yogesh Narayan Gaur
Exposing only 2 time of ahb_size is design decision but value in SFAR register should be correct.
Post by Frieder Schrempf
Thus, there should be mechanism or the entry in structure where we can have the information of the size of the connected slave device.
Because that's exactly the kind of thing I'd like to avoid. What if the device is bigger than the reserved memory region? What if the sum of all devices does not fit in there? Here I tried to support all cases by just mapping the portion of memory we need.
So IMO, there should be mechanism to have value of start address of each slave device. This might can be done from DTS entry of each slave device connected to the controller.
Let's not put that in the DT. If we really can't re-use 0 as the start address and make some ranges 0 in size, then let's reserve 2 *
->ahb_buf_size per chip, and be done with it.

This should leave us enough space in the AHB mem range to then support temporary direct mappings through the direct mapping API.

Let us take below layout of memory address space map.
QuadSPI Controller can access range from 0x2000_0000 - 0x2FFF_FFFF i.e. 256 MB address space reserved and it is having 4 slave devices connected.
These slave devices[of size 64MB, 64MB, 32MB and 64MB ] are connected at below address
0x2000_0000, 0x2400_0000, 0x2A00_0000, 0x2C00_0000
i.e. there is gap of 32MB from 0x2800_0000 to 0x29FF_FFFF.

As per my understanding of the controller, flash XX top address, register should have below values:
QUADSPI_SFA1AD - 0x0
QUADSPI_SFA2AD - 0x400_0000
QUADSPI_SFB1AD - 0xA00_0000
QUADSPI_SFB2AD - 0xC00_0000
And Register QUADSPI_SFAR should point to the range for the flash in which operation is happening.

Please check Table10-32, page 1657, in [1] for more details on flash address assignment.

But say if I assign address to register QUADSPI_SFA2AD as "0 + 2 * ->ahb_buf_size" then this address value is not correct as per the value range explained in above mentioned table.

Regards
Yogesh Gaur.

Regards,

Boris

[1] https://www.nxp.com/docs/en/reference-manual/VFXXXRM.pdf
Boris Brezillon
2018-06-19 07:28:32 UTC
Permalink
Hi Yogesh,

Could you please use a mailer that is quoting things correctly. I have
a hard time differentiating your replies from mine.

On Tue, 19 Jun 2018 07:10:37 +0000
Post by Yogesh Narayan Gaur
Let us take below layout of memory address space map.
QuadSPI Controller can access range from 0x2000_0000 - 0x2FFF_FFFF i.e. 256 MB address space reserved and it is having 4 slave devices connected.
These slave devices[of size 64MB, 64MB, 32MB and 64MB ] are connected at below address
0x2000_0000, 0x2400_0000, 0x2A00_0000, 0x2C00_0000
i.e. there is gap of 32MB from 0x2800_0000 to 0x29FF_FFFF.
Okay, I'm fine with pre-reserving 32MB per chip select.
Post by Yogesh Narayan Gaur
QUADSPI_SFA1AD - 0x0
QUADSPI_SFA2AD - 0x400_0000
QUADSPI_SFB1AD - 0xA00_0000
QUADSPI_SFB2AD - 0xC00_0000
And Register QUADSPI_SFAR should point to the range for the flash in which operation is happening.
Wait, I thought it was supposed to be an absolute address, not one
relative to the 0x20000000 offset.
Post by Yogesh Narayan Gaur
Please check Table10-32, page 1657, in [1] for more details on flash address assignment.
Yes, I still don't see where it says that having one of the range with
a zero size is forbidden, or anything mentioning a required alignment.
Post by Yogesh Narayan Gaur
But say if I assign address to register QUADSPI_SFA2AD as "0 + 2 * ->ahb_buf_size" then this address value is not correct as per the value range explained in above mentioned table.
Why? If the SFA1AD is set to zero, that should not, right?
Yogesh Narayan Gaur
2018-06-19 08:31:25 UTC
Permalink
Hi Boris,
Post by Yogesh Narayan Gaur
-----Original Message-----
Sent: Tuesday, June 19, 2018 12:59 PM
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Yogesh,
Could you please use a mailer that is quoting things correctly. I have a hard time
differentiating your replies from mine.
Sorry for this, have changed my mailer settings.
Post by Yogesh Narayan Gaur
On Tue, 19 Jun 2018 07:10:37 +0000
Post by Yogesh Narayan Gaur
Let us take below layout of memory address space map.
QuadSPI Controller can access range from 0x2000_0000 - 0x2FFF_FFFF i.e. 256
MB address space reserved and it is having 4 slave devices connected.
Post by Yogesh Narayan Gaur
These slave devices[of size 64MB, 64MB, 32MB and 64MB ] are connected
at below address 0x2000_0000, 0x2400_0000, 0x2A00_0000, 0x2C00_0000
i.e. there is gap of 32MB from 0x2800_0000 to 0x29FF_FFFF.
Okay, I'm fine with pre-reserving 32MB per chip select.
Post by Yogesh Narayan Gaur
As per my understanding of the controller, flash XX top address, register should
QUADSPI_SFA1AD - 0x0
QUADSPI_SFA2AD - 0x400_0000
QUADSPI_SFB1AD - 0xA00_0000
QUADSPI_SFB2AD - 0xC00_0000
And Register QUADSPI_SFAR should point to the range for the flash in which
operation is happening.
My mistake values of these register would be for said case are:
QUADSPI_SFA1AD - 0x400_0000
QUADSPI_SFA2AD - 0x800_0000
QUADSPI_SFB1AD - 0xC00_0000
QUADSPI_SFB2AD - 0x1000_0000

i.e. as per controller each register is having the Top address for serial flash connected at A1/A2/B1/B2 respectively.
Post by Yogesh Narayan Gaur
Wait, I thought it was supposed to be an absolute address, not one relative to
the 0x20000000 offset.
Post by Yogesh Narayan Gaur
Please check Table10-32, page 1657, in [1] for more details on flash address
assignment.
Yes, I still don't see where it says that having one of the range with a zero size is
forbidden, or anything mentioning a required alignment.
Post by Yogesh Narayan Gaur
But say if I assign address to register QUADSPI_SFA2AD as "0 + 2 * -
ahb_buf_size" then this address value is not correct as per the value range
explained in above mentioned table.
Why? If the SFA1AD is set to zero, that should not, right?
What this table says that for TOP_ADDR_MEMA1 defines the top address for flash connected at A1 and any address space between TOP_ADDR_MEMA1 and QSPI_AMBA_BASE will be routed to Serial Flash A1.
In my example case TOP_ADDR_MEMA1 is 0x400_0000
If assign value to SFAR register is "0 + 2 * ->ahb_buf_size", then this would lie in access range of Serial Flash A1 and access happens to A1 flash whereas we want access to A2 flash.

For access of serial flash A2, any address space access between TOP_ADDR_MEMA2 and TOP_ADDR_MEMA1 would be routed to serial flash A2.
Thus to access A2 flash, SFAR would be in range from 0x400_0000 and 0x800_0000

--
Regards
Yogesh Gaur
Boris Brezillon
2018-06-19 08:46:27 UTC
Permalink
On Tue, 19 Jun 2018 08:31:25 +0000
Post by Yogesh Narayan Gaur
Post by Boris Brezillon
Could you please use a mailer that is quoting things correctly. I
have a hard time differentiating your replies from mine.
Sorry for this, have changed my mailer settings.
Thanks for doing. It's still not perfect, but it's definitely better.
Post by Yogesh Narayan Gaur
Post by Boris Brezillon
On Tue, 19 Jun 2018 07:10:37 +0000
Post by Yogesh Narayan Gaur
Let us take below layout of memory address space map.
QuadSPI Controller can access range from 0x2000_0000 -
0x2FFF_FFFF i.e. 256
MB address space reserved and it is having 4 slave devices
connected.
Post by Yogesh Narayan Gaur
These slave devices[of size 64MB, 64MB, 32MB and 64MB ] are
connected at below address 0x2000_0000, 0x2400_0000, 0x2A00_0000,
0x2C00_0000 i.e. there is gap of 32MB from 0x2800_0000 to
0x29FF_FFFF.
Okay, I'm fine with pre-reserving 32MB per chip select.
Post by Yogesh Narayan Gaur
As per my understanding of the controller, flash XX top address, register should
QUADSPI_SFA1AD - 0x0
QUADSPI_SFA2AD - 0x400_0000
QUADSPI_SFB1AD - 0xA00_0000
QUADSPI_SFB2AD - 0xC00_0000
And Register QUADSPI_SFAR should point to the range for the flash in which
operation is happening.
QUADSPI_SFA1AD - 0x400_0000
QUADSPI_SFA2AD - 0x800_0000
QUADSPI_SFB1AD - 0xC00_0000
QUADSPI_SFB2AD - 0x1000_0000
i.e. as per controller each register is having the Top address for
serial flash connected at A1/A2/B1/B2 respectively.
This is still wrong ;-). I guess you mean:

QUADSPI_SFA1AD - 0x2400_0000
QUADSPI_SFA2AD - 0x2800_0000
QUADSPI_SFB1AD - 0x2C00_0000
QUADSPI_SFB2AD - 0x3000_0000
Post by Yogesh Narayan Gaur
Post by Boris Brezillon
Wait, I thought it was supposed to be an absolute address, not one
relative to the 0x20000000 offset.
Post by Yogesh Narayan Gaur
Please check Table10-32, page 1657, in [1] for more details on flash address
assignment.
Yes, I still don't see where it says that having one of the range
with a zero size is forbidden, or anything mentioning a required
alignment.
Post by Yogesh Narayan Gaur
But say if I assign address to register QUADSPI_SFA2AD as "0 + 2 * -
ahb_buf_size" then this address value is not correct as per the value range
explained in above mentioned table.
Why? If the SFA1AD is set to zero, that should not, right?
What this table says that for TOP_ADDR_MEMA1 defines the top address
for flash connected at A1 and any address space between
TOP_ADDR_MEMA1 and QSPI_AMBA_BASE will be routed to Serial Flash A1.
In my example case TOP_ADDR_MEMA1 is 0x400_0000 If assign value to
SFAR register is "0 + 2 * ->ahb_buf_size", then this would lie in
access range of Serial Flash A1 and access happens to A1 flash
whereas we want access to A2 flash.
No, not if SFA1AD is 0x20000000, because then the address range for CS0
would be 0x20000000 -> 0x20000000.

If you look at the code, you'll see that I adjust the CS mapping
dynamically, making the one being access use the range
0x20000000 -> (0x20000000 + 2 * ->ahb_buf_size) and assigning a 0-size
range for the other ones (either 0x20000000 -> 0x20000000 or
(0x20000000 + 2 * ->ahb_buf_size) -> (0x20000000 + 2 * ->ahb_buf_size))
Post by Yogesh Narayan Gaur
For access of serial flash A2, any address space access between
TOP_ADDR_MEMA2 and TOP_ADDR_MEMA1 would be routed to serial flash A2.
Thus to access A2 flash, SFAR would be in range from 0x400_0000 and 0x800_0000
I understand what you're explaining, what I don't get is why the QSPI
IP doesn't cope with a 0-size range. If you have SFA1AD set to
0x20000000 and SFA2AD set so 0x20000800, I would except any access to
the 0x20000000 -> 0x20000800 range to be routed to CS1 not CS0. But
apparently it's not working like that.
Frieder Schrempf
2018-06-26 08:58:24 UTC
Permalink
Hi Boris, hi Yogesh,

first, thank you for testing and debugging the new driver.
Post by Boris Brezillon
On Tue, 19 Jun 2018 08:31:25 +0000
[...]
Post by Boris Brezillon
Post by Yogesh Narayan Gaur
Post by Boris Brezillon
On Tue, 19 Jun 2018 07:10:37 +0000
Post by Yogesh Narayan Gaur
Let us take below layout of memory address space map.
QuadSPI Controller can access range from 0x2000_0000 -
0x2FFF_FFFF i.e. 256
MB address space reserved and it is having 4 slave devices
connected.
Post by Yogesh Narayan Gaur
These slave devices[of size 64MB, 64MB, 32MB and 64MB ] are
connected at below address 0x2000_0000, 0x2400_0000, 0x2A00_0000,
0x2C00_0000 i.e. there is gap of 32MB from 0x2800_0000 to
0x29FF_FFFF.
Okay, I'm fine with pre-reserving 32MB per chip select.
Post by Yogesh Narayan Gaur
As per my understanding of the controller, flash XX top address, register should
QUADSPI_SFA1AD - 0x0
QUADSPI_SFA2AD - 0x400_0000
QUADSPI_SFB1AD - 0xA00_0000
QUADSPI_SFB2AD - 0xC00_0000
And Register QUADSPI_SFAR should point to the range for the flash in which
operation is happening.
QUADSPI_SFA1AD - 0x400_0000
QUADSPI_SFA2AD - 0x800_0000
QUADSPI_SFB1AD - 0xC00_0000
QUADSPI_SFB2AD - 0x1000_0000
i.e. as per controller each register is having the Top address for
serial flash connected at A1/A2/B1/B2 respectively.
QUADSPI_SFA1AD - 0x2400_0000
QUADSPI_SFA2AD - 0x2800_0000
QUADSPI_SFB1AD - 0x2C00_0000
QUADSPI_SFB2AD - 0x3000_0000
Post by Yogesh Narayan Gaur
Post by Boris Brezillon
Wait, I thought it was supposed to be an absolute address, not one
relative to the 0x20000000 offset.
Post by Yogesh Narayan Gaur
Please check Table10-32, page 1657, in [1] for more details on flash address
assignment.
Yes, I still don't see where it says that having one of the range
with a zero size is forbidden, or anything mentioning a required
alignment.
Post by Yogesh Narayan Gaur
But say if I assign address to register QUADSPI_SFA2AD as "0 + 2 * -
ahb_buf_size" then this address value is not correct as per the value range
explained in above mentioned table.
Why? If the SFA1AD is set to zero, that should not, right?
What this table says that for TOP_ADDR_MEMA1 defines the top address
for flash connected at A1 and any address space between
TOP_ADDR_MEMA1 and QSPI_AMBA_BASE will be routed to Serial Flash A1.
In my example case TOP_ADDR_MEMA1 is 0x400_0000 If assign value to
SFAR register is "0 + 2 * ->ahb_buf_size", then this would lie in
access range of Serial Flash A1 and access happens to A1 flash
whereas we want access to A2 flash.
No, not if SFA1AD is 0x20000000, because then the address range for CS0
would be 0x20000000 -> 0x20000000.
If you look at the code, you'll see that I adjust the CS mapping
dynamically, making the one being access use the range
0x20000000 -> (0x20000000 + 2 * ->ahb_buf_size) and assigning a 0-size
range for the other ones (either 0x20000000 -> 0x20000000 or
(0x20000000 + 2 * ->ahb_buf_size) -> (0x20000000 + 2 * ->ahb_buf_size))
Post by Yogesh Narayan Gaur
For access of serial flash A2, any address space access between
TOP_ADDR_MEMA2 and TOP_ADDR_MEMA1 would be routed to serial flash A2.
Thus to access A2 flash, SFAR would be in range from 0x400_0000 and 0x800_0000
I understand what you're explaining, what I don't get is why the QSPI
IP doesn't cope with a 0-size range. If you have SFA1AD set to
0x20000000 and SFA2AD set so 0x20000800, I would except any access to
the 0x20000000 -> 0x20000800 range to be routed to CS1 not CS0. But
apparently it's not working like that.
But it should definitely be possible to have 0-size ranges in the
mapping. At least the RM for the i.MX6UL says:

"In case single die flash devices, TOP_ADDR_MEMA2 and
TOP_ADDR_MEMB2 should be initialized/programmed to
TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1
respectively- in effect, setting the size of these devices to 0.
This would ensure that the complete memory map is assigned
to only one flash device."

Yogesh, can you test if it works with the fixed mapping proposed above,
reserving a fixed range of 2 * ahb_buf_size for each chip?

Thanks,
Frieder
Andy Shevchenko
2018-06-08 20:27:14 UTC
Permalink
On Fri, Jun 8, 2018 at 2:54 PM, Yogesh Narayan Gaur
<***@nxp.com> wrote:

Hi Frieder,
+#define QUADSPI_MCR_RESERVED_MASK (0xF << 16)
GENMASK()
+#define QUADSPI_MCR_END_CFG_MASK (0x3 << 2)
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
+#define QUADSPI_SMPR_DDRSMP_MASK (7 << 16)
+#define QUADSPI_RBCT_WMRK_MASK 0x1F
Ditto.
+#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) (QUADSPI_LUT_BASE + \
+ QUADSPI_LUT_OFFSET + (idx) * 4)
It looks slightly better when

#define FOO \
(BAR1 + BAR2 ...)
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
+ return needs_swap_endian(q) ? __swab32(a) : a; }
func()
{
...
}

Fix this everywhere.
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
+*addr) {
+ if (q->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
+ if (q->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
Better to define ->read() and ->write() callbacks and call them unconditionally.
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
+ switch (width) {
+ return 0;
+ }
if (!is_power_of_2(width) || width >= 8)
return -E...;

return 0;

?
+
+ return -ENOTSUPP;
+}
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
+ int ret;
+
+ ret = clk_prepare_enable(q->clk_en);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(q->clk);
+ if (ret) {
+ clk_disable_unprepare(q->clk_en);
Is it needed here?
+ return ret;
+ }
+
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
+ return 0;
+}
+ qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
Redundant parens.
+ seq = seq ? 0 : 1;
seq = (seq + 1) % 2;

?
+}
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = 0;
+
+ memcpy(&val, op->data.buf.out + i,
+ min_t(unsigned int, op->data.nbytes - i, 4));
You may easily avoid this conditional on each iteration.
+
+ val = fsl_qspi_endian_xchg(q, val);
+ qspi_writel(q, val, base + QUADSPI_TBDR);
+ }
+ /* wait for the controller being ready */
FOREVER! See below.
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
Please, avoid infinite loops.

unsigned int count = 100;
...
do {
...
} while (--count);
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
Might it be racy if in between device gets a name assigned?
+ }
+ if (q->ahb_addr)
+ iounmap(q->ahb_addr);
Double unmap?
+static struct platform_driver fsl_qspi_driver = {
+ .driver = {
+ .name = "fsl-quadspi",
+ .of_match_table = fsl_qspi_dt_ids,
+ },
+ .probe = fsl_qspi_probe,
+ .remove = fsl_qspi_remove,
+ .suspend = fsl_qspi_suspend,
+ .resume = fsl_qspi_resume,
Why not in struct dev_pm_ops?
+};
+MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_AUTHOR("Boris
Wrong indentation.
--
With Best Regards,
Andy Shevchenko
Frieder Schrempf
2018-06-26 12:26:30 UTC
Permalink
Hi Andy,
Post by Andy Shevchenko
On Fri, Jun 8, 2018 at 2:54 PM, Yogesh Narayan Gaur
Hi Frieder,
+#define QUADSPI_MCR_RESERVED_MASK (0xF << 16)
GENMASK()
Ok.
Post by Andy Shevchenko
+#define QUADSPI_MCR_END_CFG_MASK (0x3 << 2)
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
+#define QUADSPI_SMPR_DDRSMP_MASK (7 << 16)
+#define QUADSPI_RBCT_WMRK_MASK 0x1F
Ditto.
Ok.
Post by Andy Shevchenko
+#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) (QUADSPI_LUT_BASE + \
+ QUADSPI_LUT_OFFSET + (idx) * 4)
It looks slightly better when
#define FOO \
(BAR1 + BAR2 ...)
Ok.
Post by Andy Shevchenko
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
+ return needs_swap_endian(q) ? __swab32(a) : a; }
func()
{
...
}
Fix this everywhere.
I will fix this.
Post by Andy Shevchenko
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
+*addr) {
+ if (q->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
+ if (q->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
Better to define ->read() and ->write() callbacks and call them unconditionally.
Ok.
Post by Andy Shevchenko
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
+ switch (width) {
+ return 0;
+ }
if (!is_power_of_2(width) || width >= 8)
return -E...;
return 0;
?
Your proposition is a bit shorter, but I think it's slightly harder to read.
Post by Andy Shevchenko
+
+ return -ENOTSUPP;
+}
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
+ int ret;
+
+ ret = clk_prepare_enable(q->clk_en);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(q->clk);
+ if (ret) {
+ clk_disable_unprepare(q->clk_en);
Is it needed here?
No, this is probably superfluous. I will remove it.
Post by Andy Shevchenko
+ return ret;
+ }
+
+ if (needs_wakeup_wait_mode(q))
+ pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
+ return 0;
+}
+ qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
Redundant parens.
Ok, I thought this is better for readability.
Post by Andy Shevchenko
+ seq = seq ? 0 : 1;
seq = (seq + 1) % 2;
?
Ok.
Post by Andy Shevchenko
+}
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ u32 val = 0;
+
+ memcpy(&val, op->data.buf.out + i,
+ min_t(unsigned int, op->data.nbytes - i, 4));
You may easily avoid this conditional on each iteration.
Do you mean something like this, or are there better ways?

u32 val = 0;

for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4)
{
memcpy(&val, op->data.buf.out + i, 4);
val = fsl_qspi_endian_xchg(q, val);
qspi_writel(q, val, base + QUADSPI_TBDR);
}

memcpy(&val, op->data.buf.out + i, op->data.nbytes);
val = fsl_qspi_endian_xchg(q, val);
qspi_writel(q, val, base + QUADSPI_TBDR);
Post by Andy Shevchenko
+
+ val = fsl_qspi_endian_xchg(q, val);
+ qspi_writel(q, val, base + QUADSPI_TBDR);
+ }
+ /* wait for the controller being ready */
FOREVER! See below.
+ do {
+ u32 status;
+
+ status = qspi_readl(q, base + QUADSPI_SR);
+ if (status &
+ (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n",
+ status);
+ continue;
+ }
+ break;
+ } while (1);
Please, avoid infinite loops.
unsigned int count = 100;
...
do {
...
} while (--count);
Ok, will change that.
Post by Andy Shevchenko
+ if (of_get_available_child_count(q->dev->of_node) == 1)
+ name = dev_name(q->dev);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s-%d", dev_name(q->dev),
+ mem->spi->chip_select);
+
+ if (!name) {
+ dev_err(dev, "failed to get memory for custom flash name\n");
+ return dev_name(q->dev);
Might it be racy if in between device gets a name assigned?
Ok, I will change that to make sure that dev_name() is only called once.
Post by Andy Shevchenko
+ }
+ if (q->ahb_addr)
+ iounmap(q->ahb_addr);
Double unmap?
Right, this is redundant. I will remove it.
Post by Andy Shevchenko
+static struct platform_driver fsl_qspi_driver = {
+ .driver = {
+ .name = "fsl-quadspi",
+ .of_match_table = fsl_qspi_dt_ids,
+ },
+ .probe = fsl_qspi_probe,
+ .remove = fsl_qspi_remove,
+ .suspend = fsl_qspi_suspend,
+ .resume = fsl_qspi_resume,
Why not in struct dev_pm_ops?
This was taken from the original driver. I will add a struct dev_pm_ops
to hold fsl_qspi_suspend() and fsl_qspi_resume().
Post by Andy Shevchenko
+};
+MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_AUTHOR("Boris
Wrong indentation.
What is wrong? Some newlines are missing here between the MODULE_
macros, but in my original patch it seems correct.

Thank you for your review,

Frieder
Boris Brezillon
2018-06-26 13:47:28 UTC
Permalink
Hi Andy,

On Tue, 26 Jun 2018 16:18:44 +0300
What is wrong? Some newlines are missing here between the MODULE_ macros,
but in my original patch it seems correct.
It should be like
MODULE_FOO(...);
MODULE_BAR(...);
MODULE_BAZ(...);
One macro — one line.
It's not Frieder's fault, it's Yogesh mailer which messed-up the
formatting. Just look at the original patch and you'll see.
Andy Shevchenko
2018-06-26 15:42:37 UTC
Permalink
On Tue, Jun 26, 2018 at 4:47 PM, Boris Brezillon
Post by Frieder Schrempf
Hi Andy,
On Tue, 26 Jun 2018 16:18:44 +0300
What is wrong? Some newlines are missing here between the MODULE_ macros,
but in my original patch it seems correct.
It should be like
MODULE_FOO(...);
MODULE_BAR(...);
MODULE_BAZ(...);
One macro — one line.
It's not Frieder's fault, it's Yogesh mailer which messed-up the
formatting. Just look at the original patch and you'll see.
One problem less, then.
Good!
--
With Best Regards,
Andy Shevchenko
Boris Brezillon
2018-06-18 19:27:40 UTC
Permalink
Yogesh,

On Wed, 30 May 2018 15:14:32 +0200
Post by Frieder Schrempf
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
+{
+ unsigned long rate = spi->max_speed_hz;
+ int ret, i;
+ u32 map_addr;
+
+ if (q->selected == spi->chip_select)
+ return;
+
+ /*
+ * In HW there can be a maximum of four chips on two buses with
+ * two chip selects on each bus. We use four chip selects in SW
+ * to differentiate between the four chips.
+ * We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
+ * the chip we want to access.
+ */
+ for (i = 0; i < 4; i++) {
+ if (i < spi->chip_select)
Can you try with:

if (i <= spi->chip_select)

and let me know if it fixes the problem you have when CS != 0?
Post by Frieder Schrempf
+ map_addr = q->memmap_phy;
+ else
+ map_addr = q->memmap_phy +
+ 2 * q->devtype_data->ahb_buf_size;
+
+ qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
+ }
+
+ if (needs_4x_clock(q))
+ rate *= 4;
+
+ fsl_qspi_clk_disable_unprep(q);
+
+ ret = clk_set_rate(q->clk, rate);
+ if (ret)
+ return;
+
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return;
+
+ q->selected = spi->chip_select;
+}
Frieder Schrempf
2018-05-30 13:14:36 UTC
Permalink
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f70507a..d07a535 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -111,7 +111,6 @@ CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_SPI_NOR=y
-CONFIG_SPI_FSL_QUADSPI=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_BLOCK=y
@@ -199,6 +198,7 @@ CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_GPIO=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
+CONFIG_SPI_FSL_QSPI=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_IMX=y
CONFIG_SPI_FSL_DSPI=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 7b2283a..1423ec3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -191,7 +191,6 @@ CONFIG_MTD_NAND_BRCMNAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_SPI_NOR=y
-CONFIG_SPI_FSL_QUADSPI=m
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -379,6 +378,7 @@ CONFIG_SPI_BCM2835=y
CONFIG_SPI_BCM2835AUX=y
CONFIG_SPI_CADENCE=y
CONFIG_SPI_DAVINCI=y
+CONFIG_SPI_FSL_QSPI=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_DSPI=m
CONFIG_SPI_OMAP24XX=y
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:31 UTC
Permalink
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when controller drivers are
ported from the MTD to the SPI layer.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
drivers/mtd/devices/m25p80.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 3dc022d..e1ee3b9 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -199,8 +199,7 @@ static int m25p_probe(struct spi_mem *spimem)
hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
}

- if (data && data->name)
- nor->mtd.name = data->name;
+ nor->mtd.name = spi_mem_get_name(spimem);

/* For some (historical?) reason many platforms provide two different
* names in flash_platform_data: "name" and "type". Quite often name is
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:40 UTC
Permalink
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9051a9c..22cfc8d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5732,9 +5732,9 @@ F: Documentation/devicetree/bindings/powerpc/fsl/fman.txt

FREESCALE QUAD SPI DRIVER
M: Han Xu <***@nxp.com>
-L: linux-***@lists.infradead.org
+L: linux-***@vger.kernel.org
S: Maintained
-F: drivers/mtd/spi-nor/fsl-quadspi.c
+F: drivers/spi/spi-fsl-qspi.c

FREESCALE QUICC ENGINE LIBRARY
M: Qiang Zhao <***@nxp.com>
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:35 UTC
Permalink
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.

Also the properties 'num-cs' and 'bus-num' were never read by the
driver and can be removed.

The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking fsl-ls1046a-rdb.dts.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 3 ++-
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 4 ++--
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 6 ++++--
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 4 ++++
4 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 6341281..31e7b31 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -170,7 +170,6 @@
};

&qspi {
- bus-num = <0>;
status = "okay";

qflash0: ***@0 {
@@ -178,6 +177,8 @@
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index 434383b..dc10105 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -198,8 +198,6 @@
};

&qspi {
- num-cs = <2>;
- bus-num = <0>;
status = "okay";

qflash0: ***@0 {
@@ -207,6 +205,8 @@
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 5dc2782..1848c33 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -136,8 +136,6 @@
};

&qspi {
- num-cs = <2>;
- bus-num = <0>;
status = "okay";

qflash0: ***@0 {
@@ -145,6 +143,8 @@
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};

@@ -153,6 +153,8 @@
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <1>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
index 1de6188..fc62ed9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
@@ -170,6 +170,8 @@
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};
flash2: ***@2 {
@@ -177,6 +179,8 @@
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <2>;
};
};
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:39 UTC
Permalink
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.

The driver now uses the 'reg' property to determine the bus and
the chipselect.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 136ebfa..871189e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -247,7 +247,6 @@
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
big-endian;
- fsl,qspi-has-second-chip;
status = "disabled";
};
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:38 UTC
Permalink
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.

The driver now uses the 'reg' property to determine the bus and
the chipselect.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 -
1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index 6a83f30..d3a1a73 100644
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -203,7 +203,6 @@
};

&qspi {
- fsl,qspi-has-second-chip;
status = "okay";

flash: ***@0 {
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:34 UTC
Permalink
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.

Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read by the driver and
can be removed.

The 'reg' properties are adjusted to reflect the what bus and
chipselect the flash is connected to, as the new driver needs
this information.

The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking ls1021a-moxa-uc-8410a.dts.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 8 ++++++--
arch/arm/boot/dts/imx6sx-sdb.dts | 8 ++++++--
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 ++
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 5 ++---
4 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index e3533e7..1a6f680 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -131,13 +131,17 @@
#size-cells = <1>;
compatible = "spansion,s25fl128s", "jedec,spi-nor";
spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};

- flash1: ***@1 {
- reg = <1>;
+ flash1: ***@2 {
+ reg = <2>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s", "jedec,spi-nor";
spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 6dd9beb..9acfda8 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -117,15 +117,19 @@
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};

- flash1: ***@1 {
+ flash1: ***@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
- reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <2>;
};
};

diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index 32a0723..c2c9a2a 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -176,6 +176,8 @@
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};
};
diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index d01f64b..6a83f30 100644
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -203,9 +203,6 @@
};

&qspi {
- bus-num = <0>;
- fsl,spi-num-chipselects = <2>;
- fsl,spi-flash-chipselects = <0>;
fsl,qspi-has-second-chip;
status = "okay";

@@ -214,6 +211,8 @@
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;

***@0 {
--
2.7.4
Boris Brezillon
2018-05-30 15:10:57 UTC
Permalink
On Wed, 30 May 2018 15:14:34 +0200
Post by Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
We should try to keep the current behavior even when
spi-[rx/tx]-bus-width are not defined. How about considering
spi-[rx/tx]-bus-width as board constraints and then let the core pick
the best mode based on these constraints plus the SPI NOR chip
limitations.
Post by Frieder Schrempf
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read by the driver and
can be removed.
The 'reg' properties are adjusted to reflect the what bus and
chipselect the flash is connected to, as the new driver needs
this information.
The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking ls1021a-moxa-uc-8410a.dts.
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 8 ++++++--
arch/arm/boot/dts/imx6sx-sdb.dts | 8 ++++++--
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 ++
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 5 ++---
4 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index e3533e7..1a6f680 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -131,13 +131,17 @@
#size-cells = <1>;
compatible = "spansion,s25fl128s", "jedec,spi-nor";
spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
- reg = <1>;
+ reg = <2>;
Hm, you're breaking backward compat here. Can we try to re-use the
old numbering scheme instead of patching all DTs?
Frieder Schrempf
2018-06-01 09:27:13 UTC
Permalink
Hi Boris,
Post by Boris Brezillon
On Wed, 30 May 2018 15:14:34 +0200
Post by Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
We should try to keep the current behavior even when
spi-[rx/tx]-bus-width are not defined. How about considering
spi-[rx/tx]-bus-width as board constraints and then let the core pick
the best mode based on these constraints plus the SPI NOR chip
limitations.
Ok, I'll try to adjust this, so we can leave spi-[rx/tx]-bus-width
undefined and still get quad mode as default if possible.
Post by Boris Brezillon
Post by Frieder Schrempf
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read by the driver and
can be removed.
The 'reg' properties are adjusted to reflect the what bus and
chipselect the flash is connected to, as the new driver needs
this information.
The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking ls1021a-moxa-uc-8410a.dts.
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 8 ++++++--
arch/arm/boot/dts/imx6sx-sdb.dts | 8 ++++++--
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 ++
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 5 ++---
4 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index e3533e7..1a6f680 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -131,13 +131,17 @@
#size-cells = <1>;
compatible = "spansion,s25fl128s", "jedec,spi-nor";
spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
- reg = <1>;
+ reg = <2>;
Hm, you're breaking backward compat here. Can we try to re-use the
old numbering scheme instead of patching all DTs?
Unfortunately in the current setup, the definitions for the reg property
are already broken.

For example imx6sx-sdb.dts seems to have one chip connected on bus A,
CS0 and one on bus B, CS0. It has reg set to 0 for the first and 1 for
the second chip.

While fsl-ls208xa-qds.dtsi uses the same hw setup, but has reg set to 0
and 2.

So either way we need to change the reg property at some place.
So the best approach in my opinion is to fix the definitions to use a
single scheme and while at it also remove the fsl,qspi-has-second-chip
property, that is not needed if a single consistent scheme for the reg
properties is used.

Regards,

Frieder
Frieder Schrempf
2018-05-30 13:14:37 UTC
Permalink
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
drivers/mtd/spi-nor/Kconfig | 9 -
drivers/mtd/spi-nor/Makefile | 1 -
drivers/mtd/spi-nor/fsl-quadspi.c | 1206 --------------------------------
3 files changed, 1216 deletions(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index c493b82..169990b 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
device with a Cadence QSPI controller and want to access the
Flash as an MTD device.

-config SPI_FSL_QUADSPI
- tristate "Freescale Quad SPI controller"
- depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
- depends on HAS_IOMEM
- help
- This enables support for the Quad SPI controller in master mode.
- This controller does not support generic SPI. It only supports
- SPI NOR.
-
config SPI_HISI_SFC
tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index f4c61d2..3f160c2e3 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
-obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
deleted file mode 100644
index 3e3c0bb..0000000
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ /dev/null
@@ -1,1206 +0,0 @@
-/*
- * Freescale QuadSPI driver.
- *
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/timer.h>
-#include <linux/jiffies.h>
-#include <linux/completion.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/spi-nor.h>
-#include <linux/mutex.h>
-#include <linux/pm_qos.h>
-#include <linux/sizes.h>
-
-/* Controller needs driver to swap endian */
-#define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
-/* Controller needs 4x internal clock */
-#define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
-/*
- * TKT253890, Controller needs driver to fill txfifo till 16 byte to
- * trigger data transfer even though extern data will not transferred.
- */
-#define QUADSPI_QUIRK_TKT253890 (1 << 2)
-/* Controller cannot wake up from wait mode, TKT245618 */
-#define QUADSPI_QUIRK_TKT245618 (1 << 3)
-
-/* The registers */
-#define QUADSPI_MCR 0x00
-#define QUADSPI_MCR_RESERVED_SHIFT 16
-#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
-#define QUADSPI_MCR_MDIS_SHIFT 14
-#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
-#define QUADSPI_MCR_CLR_TXF_SHIFT 11
-#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
-#define QUADSPI_MCR_CLR_RXF_SHIFT 10
-#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
-#define QUADSPI_MCR_DDR_EN_SHIFT 7
-#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
-#define QUADSPI_MCR_END_CFG_SHIFT 2
-#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
-#define QUADSPI_MCR_SWRSTHD_SHIFT 1
-#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
-#define QUADSPI_MCR_SWRSTSD_SHIFT 0
-#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
-
-#define QUADSPI_IPCR 0x08
-#define QUADSPI_IPCR_SEQID_SHIFT 24
-#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
-
-#define QUADSPI_BUF0CR 0x10
-#define QUADSPI_BUF1CR 0x14
-#define QUADSPI_BUF2CR 0x18
-#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
-
-#define QUADSPI_BUF3CR 0x1c
-#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
-#define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
-#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
-#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
-
-#define QUADSPI_BFGENCR 0x20
-#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
-#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
-#define QUADSPI_BFGENCR_SEQID_SHIFT 12
-#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
-
-#define QUADSPI_BUF0IND 0x30
-#define QUADSPI_BUF1IND 0x34
-#define QUADSPI_BUF2IND 0x38
-#define QUADSPI_SFAR 0x100
-
-#define QUADSPI_SMPR 0x108
-#define QUADSPI_SMPR_DDRSMP_SHIFT 16
-#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
-#define QUADSPI_SMPR_FSDLY_SHIFT 6
-#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
-#define QUADSPI_SMPR_FSPHS_SHIFT 5
-#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
-#define QUADSPI_SMPR_HSENA_SHIFT 0
-#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
-
-#define QUADSPI_RBSR 0x10c
-#define QUADSPI_RBSR_RDBFL_SHIFT 8
-#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
-
-#define QUADSPI_RBCT 0x110
-#define QUADSPI_RBCT_WMRK_MASK 0x1F
-#define QUADSPI_RBCT_RXBRD_SHIFT 8
-#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
-
-#define QUADSPI_TBSR 0x150
-#define QUADSPI_TBDR 0x154
-#define QUADSPI_SR 0x15c
-#define QUADSPI_SR_IP_ACC_SHIFT 1
-#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
-#define QUADSPI_SR_AHB_ACC_SHIFT 2
-#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
-
-#define QUADSPI_FR 0x160
-#define QUADSPI_FR_TFF_MASK 0x1
-
-#define QUADSPI_SFA1AD 0x180
-#define QUADSPI_SFA2AD 0x184
-#define QUADSPI_SFB1AD 0x188
-#define QUADSPI_SFB2AD 0x18c
-#define QUADSPI_RBDR 0x200
-
-#define QUADSPI_LUTKEY 0x300
-#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
-
-#define QUADSPI_LCKCR 0x304
-#define QUADSPI_LCKER_LOCK 0x1
-#define QUADSPI_LCKER_UNLOCK 0x2
-
-#define QUADSPI_RSER 0x164
-#define QUADSPI_RSER_TFIE (0x1 << 0)
-
-#define QUADSPI_LUT_BASE 0x310
-
-/*
- * The definition of the LUT register shows below:
- *
- * ---------------------------------------------------
- * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
- * ---------------------------------------------------
- */
-#define OPRND0_SHIFT 0
-#define PAD0_SHIFT 8
-#define INSTR0_SHIFT 10
-#define OPRND1_SHIFT 16
-
-/* Instruction set for the LUT register. */
-#define LUT_STOP 0
-#define LUT_CMD 1
-#define LUT_ADDR 2
-#define LUT_DUMMY 3
-#define LUT_MODE 4
-#define LUT_MODE2 5
-#define LUT_MODE4 6
-#define LUT_FSL_READ 7
-#define LUT_FSL_WRITE 8
-#define LUT_JMP_ON_CS 9
-#define LUT_ADDR_DDR 10
-#define LUT_MODE_DDR 11
-#define LUT_MODE2_DDR 12
-#define LUT_MODE4_DDR 13
-#define LUT_FSL_READ_DDR 14
-#define LUT_FSL_WRITE_DDR 15
-#define LUT_DATA_LEARN 16
-
-/*
- * The PAD definitions for LUT register.
- *
- * The pad stands for the lines number of IO[0:3].
- * For example, the Quad read need four IO lines, so you should
- * set LUT_PAD4 which means we use four IO lines.
- */
-#define LUT_PAD1 0
-#define LUT_PAD2 1
-#define LUT_PAD4 2
-
-/* Oprands for the LUT register. */
-#define ADDR24BIT 0x18
-#define ADDR32BIT 0x20
-
-/* Macros for constructing the LUT register. */
-#define LUT0(ins, pad, opr) \
- (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
- ((LUT_##ins) << INSTR0_SHIFT))
-
-#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
-
-/* other macros for LUT register. */
-#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
-#define QUADSPI_LUT_NUM 64
-
-/* SEQID -- we can have 16 seqids at most. */
-#define SEQID_READ 0
-#define SEQID_WREN 1
-#define SEQID_WRDI 2
-#define SEQID_RDSR 3
-#define SEQID_SE 4
-#define SEQID_CHIP_ERASE 5
-#define SEQID_PP 6
-#define SEQID_RDID 7
-#define SEQID_WRSR 8
-#define SEQID_RDCR 9
-#define SEQID_EN4B 10
-#define SEQID_BRWR 11
-
-#define QUADSPI_MIN_IOMAP SZ_4M
-
-enum fsl_qspi_devtype {
- FSL_QUADSPI_VYBRID,
- FSL_QUADSPI_IMX6SX,
- FSL_QUADSPI_IMX7D,
- FSL_QUADSPI_IMX6UL,
- FSL_QUADSPI_LS1021A,
-};
-
-struct fsl_qspi_devtype_data {
- enum fsl_qspi_devtype devtype;
- int rxfifo;
- int txfifo;
- int ahb_buf_size;
- int driver_data;
-};
-
-static const struct fsl_qspi_devtype_data vybrid_data = {
- .devtype = FSL_QUADSPI_VYBRID,
- .rxfifo = 128,
- .txfifo = 64,
- .ahb_buf_size = 1024,
- .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
-};
-
-static const struct fsl_qspi_devtype_data imx6sx_data = {
- .devtype = FSL_QUADSPI_IMX6SX,
- .rxfifo = 128,
- .txfifo = 512,
- .ahb_buf_size = 1024,
- .driver_data = QUADSPI_QUIRK_4X_INT_CLK
- | QUADSPI_QUIRK_TKT245618,
-};
-
-static const struct fsl_qspi_devtype_data imx7d_data = {
- .devtype = FSL_QUADSPI_IMX7D,
- .rxfifo = 512,
- .txfifo = 512,
- .ahb_buf_size = 1024,
- .driver_data = QUADSPI_QUIRK_TKT253890
- | QUADSPI_QUIRK_4X_INT_CLK,
-};
-
-static const struct fsl_qspi_devtype_data imx6ul_data = {
- .devtype = FSL_QUADSPI_IMX6UL,
- .rxfifo = 128,
- .txfifo = 512,
- .ahb_buf_size = 1024,
- .driver_data = QUADSPI_QUIRK_TKT253890
- | QUADSPI_QUIRK_4X_INT_CLK,
-};
-
-static struct fsl_qspi_devtype_data ls1021a_data = {
- .devtype = FSL_QUADSPI_LS1021A,
- .rxfifo = 128,
- .txfifo = 64,
- .ahb_buf_size = 1024,
- .driver_data = 0,
-};
-
-#define FSL_QSPI_MAX_CHIP 4
-struct fsl_qspi {
- struct spi_nor nor[FSL_QSPI_MAX_CHIP];
- void __iomem *iobase;
- void __iomem *ahb_addr;
- u32 memmap_phy;
- u32 memmap_offs;
- u32 memmap_len;
- struct clk *clk, *clk_en;
- struct device *dev;
- struct completion c;
- const struct fsl_qspi_devtype_data *devtype_data;
- u32 nor_size;
- u32 nor_num;
- u32 clk_rate;
- unsigned int chip_base_addr; /* We may support two chips. */
- bool has_second_chip;
- bool big_endian;
- struct mutex lock;
- struct pm_qos_request pm_qos_req;
-};
-
-static inline int needs_swap_endian(struct fsl_qspi *q)
-{
- return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
-}
-
-static inline int needs_4x_clock(struct fsl_qspi *q)
-{
- return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
-}
-
-static inline int needs_fill_txfifo(struct fsl_qspi *q)
-{
- return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
-}
-
-static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
-{
- return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
-}
-
-/*
- * R/W functions for big- or little-endian registers:
- * The qSPI controller's endian is independent of the CPU core's endian.
- * So far, although the CPU core is little-endian but the qSPI have two
- * versions for big-endian and little-endian.
- */
-static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
-{
- if (q->big_endian)
- iowrite32be(val, addr);
- else
- iowrite32(val, addr);
-}
-
-static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
-{
- if (q->big_endian)
- return ioread32be(addr);
- else
- return ioread32(addr);
-}
-
-/*
- * An IC bug makes us to re-arrange the 32-bit data.
- * The following chips, such as IMX6SLX, have fixed this bug.
- */
-static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
-{
- return needs_swap_endian(q) ? __swab32(a) : a;
-}
-
-static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
-{
- qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
- qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
-}
-
-static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
-{
- qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
- qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
-}
-
-static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
-{
- struct fsl_qspi *q = dev_id;
- u32 reg;
-
- /* clear interrupt */
- reg = qspi_readl(q, q->iobase + QUADSPI_FR);
- qspi_writel(q, reg, q->iobase + QUADSPI_FR);
-
- if (reg & QUADSPI_FR_TFF_MASK)
- complete(&q->c);
-
- dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
- return IRQ_HANDLED;
-}
-
-static void fsl_qspi_init_lut(struct fsl_qspi *q)
-{
- void __iomem *base = q->iobase;
- int rxfifo = q->devtype_data->rxfifo;
- u32 lut_base;
- int i;
-
- struct spi_nor *nor = &q->nor[0];
- u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
- u8 read_op = nor->read_opcode;
- u8 read_dm = nor->read_dummy;
-
- fsl_qspi_unlock_lut(q);
-
- /* Clear all the LUT table */
- for (i = 0; i < QUADSPI_LUT_NUM; i++)
- qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
-
- /* Read */
- lut_base = SEQID_READ * 4;
-
- qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
- base + QUADSPI_LUT(lut_base));
- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
- LUT1(FSL_READ, PAD4, rxfifo),
- base + QUADSPI_LUT(lut_base + 1));
-
- /* Write enable */
- lut_base = SEQID_WREN * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
- base + QUADSPI_LUT(lut_base));
-
- /* Page Program */
- lut_base = SEQID_PP * 4;
-
- qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
- LUT1(ADDR, PAD1, addrlen),
- base + QUADSPI_LUT(lut_base));
- qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
- base + QUADSPI_LUT(lut_base + 1));
-
- /* Read Status */
- lut_base = SEQID_RDSR * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
- LUT1(FSL_READ, PAD1, 0x1),
- base + QUADSPI_LUT(lut_base));
-
- /* Erase a sector */
- lut_base = SEQID_SE * 4;
-
- qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
- LUT1(ADDR, PAD1, addrlen),
- base + QUADSPI_LUT(lut_base));
-
- /* Erase the whole chip */
- lut_base = SEQID_CHIP_ERASE * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
- base + QUADSPI_LUT(lut_base));
-
- /* READ ID */
- lut_base = SEQID_RDID * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
- LUT1(FSL_READ, PAD1, 0x8),
- base + QUADSPI_LUT(lut_base));
-
- /* Write Register */
- lut_base = SEQID_WRSR * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
- LUT1(FSL_WRITE, PAD1, 0x2),
- base + QUADSPI_LUT(lut_base));
-
- /* Read Configuration Register */
- lut_base = SEQID_RDCR * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
- LUT1(FSL_READ, PAD1, 0x1),
- base + QUADSPI_LUT(lut_base));
-
- /* Write disable */
- lut_base = SEQID_WRDI * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
- base + QUADSPI_LUT(lut_base));
-
- /* Enter 4 Byte Mode (Micron) */
- lut_base = SEQID_EN4B * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
- base + QUADSPI_LUT(lut_base));
-
- /* Enter 4 Byte Mode (Spansion) */
- lut_base = SEQID_BRWR * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
- base + QUADSPI_LUT(lut_base));
-
- fsl_qspi_lock_lut(q);
-}
-
-/* Get the SEQID for the command */
-static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
-{
- switch (cmd) {
- case SPINOR_OP_READ_1_1_4:
- return SEQID_READ;
- case SPINOR_OP_WREN:
- return SEQID_WREN;
- case SPINOR_OP_WRDI:
- return SEQID_WRDI;
- case SPINOR_OP_RDSR:
- return SEQID_RDSR;
- case SPINOR_OP_SE:
- return SEQID_SE;
- case SPINOR_OP_CHIP_ERASE:
- return SEQID_CHIP_ERASE;
- case SPINOR_OP_PP:
- return SEQID_PP;
- case SPINOR_OP_RDID:
- return SEQID_RDID;
- case SPINOR_OP_WRSR:
- return SEQID_WRSR;
- case SPINOR_OP_RDCR:
- return SEQID_RDCR;
- case SPINOR_OP_EN4B:
- return SEQID_EN4B;
- case SPINOR_OP_BRWR:
- return SEQID_BRWR;
- default:
- if (cmd == q->nor[0].erase_opcode)
- return SEQID_SE;
- dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
- break;
- }
- return -EINVAL;
-}
-
-static int
-fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
-{
- void __iomem *base = q->iobase;
- int seqid;
- u32 reg, reg2;
- int err;
-
- init_completion(&q->c);
- dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
- q->chip_base_addr, addr, len, cmd);
-
- /* save the reg */
- reg = qspi_readl(q, base + QUADSPI_MCR);
-
- qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
- base + QUADSPI_SFAR);
- qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
- base + QUADSPI_RBCT);
- qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
-
- do {
- reg2 = qspi_readl(q, base + QUADSPI_SR);
- if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
- udelay(1);
- dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
- continue;
- }
- break;
- } while (1);
-
- /* trigger the LUT now */
- seqid = fsl_qspi_get_seqid(q, cmd);
- qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
- base + QUADSPI_IPCR);
-
- /* Wait for the interrupt. */
- if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
- dev_err(q->dev,
- "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
- cmd, addr, qspi_readl(q, base + QUADSPI_FR),
- qspi_readl(q, base + QUADSPI_SR));
- err = -ETIMEDOUT;
- } else {
- err = 0;
- }
-
- /* restore the MCR */
- qspi_writel(q, reg, base + QUADSPI_MCR);
-
- return err;
-}
-
-/* Read out the data from the QUADSPI_RBDR buffer registers. */
-static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
-{
- u32 tmp;
- int i = 0;
-
- while (len > 0) {
- tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
- tmp = fsl_qspi_endian_xchg(q, tmp);
- dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
- q->chip_base_addr, tmp);
-
- if (len >= 4) {
- *((u32 *)rxbuf) = tmp;
- rxbuf += 4;
- } else {
- memcpy(rxbuf, &tmp, len);
- break;
- }
-
- len -= 4;
- i++;
- }
-}
-
-/*
- * If we have changed the content of the flash by writing or erasing,
- * we need to invalidate the AHB buffer. If we do not do so, we may read out
- * the wrong data. The spec tells us reset the AHB domain and Serial Flash
- * domain at the same time.
- */
-static inline void fsl_qspi_invalid(struct fsl_qspi *q)
-{
- u32 reg;
-
- reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
- reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
- qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
-
- /*
- * The minimum delay : 1 AHB + 2 SFCK clocks.
- * Delay 1 us is enough.
- */
- udelay(1);
-
- reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
- qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
-}
-
-static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
- u8 opcode, unsigned int to, u32 *txbuf,
- unsigned count)
-{
- int ret, i, j;
- u32 tmp;
-
- dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
- q->chip_base_addr, to, count);
-
- /* clear the TX FIFO. */
- tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
- qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
-
- /* fill the TX data to the FIFO */
- for (j = 0, i = ((count + 3) / 4); j < i; j++) {
- tmp = fsl_qspi_endian_xchg(q, *txbuf);
- qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
- txbuf++;
- }
-
- /* fill the TXFIFO upto 16 bytes for i.MX7d */
- if (needs_fill_txfifo(q))
- for (; i < 4; i++)
- qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
-
- /* Trigger it */
- ret = fsl_qspi_runcmd(q, opcode, to, count);
-
- if (ret == 0)
- return count;
-
- return ret;
-}
-
-static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
-{
- int nor_size = q->nor_size;
- void __iomem *base = q->iobase;
-
- qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
- qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
- qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
- qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
-}
-
-/*
- * There are two different ways to read out the data from the flash:
- * the "IP Command Read" and the "AHB Command Read".
- *
- * The IC guy suggests we use the "AHB Command Read" which is faster
- * then the "IP Command Read". (What's more is that there is a bug in
- * the "IP Command Read" in the Vybrid.)
- *
- * After we set up the registers for the "AHB Command Read", we can use
- * the memcpy to read the data directly. A "missed" access to the buffer
- * causes the controller to clear the buffer, and use the sequence pointed
- * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
- */
-static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
-{
- void __iomem *base = q->iobase;
- int seqid;
-
- /* AHB configuration for access buffer 0/1/2 .*/
- qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
- qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
- qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
- /*
- * Set ADATSZ with the maximum AHB buffer size to improve the
- * read performance.
- */
- qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
- ((q->devtype_data->ahb_buf_size / 8)
- << QUADSPI_BUF3CR_ADATSZ_SHIFT),
- base + QUADSPI_BUF3CR);
-
- /* We only use the buffer3 */
- qspi_writel(q, 0, base + QUADSPI_BUF0IND);
- qspi_writel(q, 0, base + QUADSPI_BUF1IND);
- qspi_writel(q, 0, base + QUADSPI_BUF2IND);
-
- /* Set the default lut sequence for AHB Read. */
- seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
- qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
- q->iobase + QUADSPI_BFGENCR);
-}
-
-/* This function was used to prepare and enable QSPI clock */
-static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
-{
- int ret;
-
- ret = clk_prepare_enable(q->clk_en);
- if (ret)
- return ret;
-
- ret = clk_prepare_enable(q->clk);
- if (ret) {
- clk_disable_unprepare(q->clk_en);
- return ret;
- }
-
- if (needs_wakeup_wait_mode(q))
- pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
-
- return 0;
-}
-
-/* This function was used to disable and unprepare QSPI clock */
-static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
-{
- if (needs_wakeup_wait_mode(q))
- pm_qos_remove_request(&q->pm_qos_req);
-
- clk_disable_unprepare(q->clk);
- clk_disable_unprepare(q->clk_en);
-
-}
-
-/* We use this function to do some basic init for spi_nor_scan(). */
-static int fsl_qspi_nor_setup(struct fsl_qspi *q)
-{
- void __iomem *base = q->iobase;
- u32 reg;
- int ret;
-
- /* disable and unprepare clock to avoid glitch pass to controller */
- fsl_qspi_clk_disable_unprep(q);
-
- /* the default frequency, we will change it in the future. */
- ret = clk_set_rate(q->clk, 66000000);
- if (ret)
- return ret;
-
- ret = fsl_qspi_clk_prep_enable(q);
- if (ret)
- return ret;
-
- /* Reset the module */
- qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
- base + QUADSPI_MCR);
- udelay(1);
-
- /* Init the LUT table. */
- fsl_qspi_init_lut(q);
-
- /* Disable the module */
- qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
- base + QUADSPI_MCR);
-
- reg = qspi_readl(q, base + QUADSPI_SMPR);
- qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
- | QUADSPI_SMPR_FSPHS_MASK
- | QUADSPI_SMPR_HSENA_MASK
- | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
-
- /* Enable the module */
- qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
- base + QUADSPI_MCR);
-
- /* clear all interrupt status */
- qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
-
- /* enable the interrupt */
- qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
-
- return 0;
-}
-
-static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
-{
- unsigned long rate = q->clk_rate;
- int ret;
-
- if (needs_4x_clock(q))
- rate *= 4;
-
- /* disable and unprepare clock to avoid glitch pass to controller */
- fsl_qspi_clk_disable_unprep(q);
-
- ret = clk_set_rate(q->clk, rate);
- if (ret)
- return ret;
-
- ret = fsl_qspi_clk_prep_enable(q);
- if (ret)
- return ret;
-
- /* Init the LUT table again. */
- fsl_qspi_init_lut(q);
-
- /* Init for AHB read */
- fsl_qspi_init_abh_read(q);
-
- return 0;
-}
-
-static const struct of_device_id fsl_qspi_dt_ids[] = {
- { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
- { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
- { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
- { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
- { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-
-static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
-{
- q->chip_base_addr = q->nor_size * (nor - q->nor);
-}
-
-static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
-{
- int ret;
- struct fsl_qspi *q = nor->priv;
-
- ret = fsl_qspi_runcmd(q, opcode, 0, len);
- if (ret)
- return ret;
-
- fsl_qspi_read_data(q, len, buf);
- return 0;
-}
-
-static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
-{
- struct fsl_qspi *q = nor->priv;
- int ret;
-
- if (!buf) {
- ret = fsl_qspi_runcmd(q, opcode, 0, 1);
- if (ret)
- return ret;
-
- if (opcode == SPINOR_OP_CHIP_ERASE)
- fsl_qspi_invalid(q);
-
- } else if (len > 0) {
- ret = fsl_qspi_nor_write(q, nor, opcode, 0,
- (u32 *)buf, len);
- if (ret > 0)
- return 0;
- } else {
- dev_err(q->dev, "invalid cmd %d\n", opcode);
- ret = -EINVAL;
- }
-
- return ret;
-}
-
-static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
- size_t len, const u_char *buf)
-{
- struct fsl_qspi *q = nor->priv;
- ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
- (u32 *)buf, len);
-
- /* invalid the data in the AHB buffer. */
- fsl_qspi_invalid(q);
- return ret;
-}
-
-static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
- size_t len, u_char *buf)
-{
- struct fsl_qspi *q = nor->priv;
- u8 cmd = nor->read_opcode;
-
- /* if necessary,ioremap buffer before AHB read, */
- if (!q->ahb_addr) {
- q->memmap_offs = q->chip_base_addr + from;
- q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
-
- q->ahb_addr = ioremap_nocache(
- q->memmap_phy + q->memmap_offs,
- q->memmap_len);
- if (!q->ahb_addr) {
- dev_err(q->dev, "ioremap failed\n");
- return -ENOMEM;
- }
- /* ioremap if the data requested is out of range */
- } else if (q->chip_base_addr + from < q->memmap_offs
- || q->chip_base_addr + from + len >
- q->memmap_offs + q->memmap_len) {
- iounmap(q->ahb_addr);
-
- q->memmap_offs = q->chip_base_addr + from;
- q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
- q->ahb_addr = ioremap_nocache(
- q->memmap_phy + q->memmap_offs,
- q->memmap_len);
- if (!q->ahb_addr) {
- dev_err(q->dev, "ioremap failed\n");
- return -ENOMEM;
- }
- }
-
- dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
- cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
- len);
-
- /* Read out the data directly from the AHB buffer.*/
- memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
- len);
-
- return len;
-}
-
-static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
-{
- struct fsl_qspi *q = nor->priv;
- int ret;
-
- dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
- nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
-
- ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
- if (ret)
- return ret;
-
- fsl_qspi_invalid(q);
- return 0;
-}
-
-static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
-{
- struct fsl_qspi *q = nor->priv;
- int ret;
-
- mutex_lock(&q->lock);
-
- ret = fsl_qspi_clk_prep_enable(q);
- if (ret)
- goto err_mutex;
-
- fsl_qspi_set_base_addr(q, nor);
- return 0;
-
-err_mutex:
- mutex_unlock(&q->lock);
- return ret;
-}
-
-static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
-{
- struct fsl_qspi *q = nor->priv;
-
- fsl_qspi_clk_disable_unprep(q);
- mutex_unlock(&q->lock);
-}
-
-static int fsl_qspi_probe(struct platform_device *pdev)
-{
- const struct spi_nor_hwcaps hwcaps = {
- .mask = SNOR_HWCAPS_READ_1_1_4 |
- SNOR_HWCAPS_PP,
- };
- struct device_node *np = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- struct fsl_qspi *q;
- struct resource *res;
- struct spi_nor *nor;
- struct mtd_info *mtd;
- int ret, i = 0;
-
- q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
- if (!q)
- return -ENOMEM;
-
- q->nor_num = of_get_child_count(dev->of_node);
- if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
- return -ENODEV;
-
- q->dev = dev;
- q->devtype_data = of_device_get_match_data(dev);
- if (!q->devtype_data)
- return -ENODEV;
- platform_set_drvdata(pdev, q);
-
- /* find the resources */
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
- q->iobase = devm_ioremap_resource(dev, res);
- if (IS_ERR(q->iobase))
- return PTR_ERR(q->iobase);
-
- q->big_endian = of_property_read_bool(np, "big-endian");
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "QuadSPI-memory");
- if (!devm_request_mem_region(dev, res->start, resource_size(res),
- res->name)) {
- dev_err(dev, "can't request region for resource %pR\n", res);
- return -EBUSY;
- }
-
- q->memmap_phy = res->start;
-
- /* find the clocks */
- q->clk_en = devm_clk_get(dev, "qspi_en");
- if (IS_ERR(q->clk_en))
- return PTR_ERR(q->clk_en);
-
- q->clk = devm_clk_get(dev, "qspi");
- if (IS_ERR(q->clk))
- return PTR_ERR(q->clk);
-
- ret = fsl_qspi_clk_prep_enable(q);
- if (ret) {
- dev_err(dev, "can not enable the clock\n");
- goto clk_failed;
- }
-
- /* find the irq */
- ret = platform_get_irq(pdev, 0);
- if (ret < 0) {
- dev_err(dev, "failed to get the irq: %d\n", ret);
- goto irq_failed;
- }
-
- ret = devm_request_irq(dev, ret,
- fsl_qspi_irq_handler, 0, pdev->name, q);
- if (ret) {
- dev_err(dev, "failed to request irq: %d\n", ret);
- goto irq_failed;
- }
-
- ret = fsl_qspi_nor_setup(q);
- if (ret)
- goto irq_failed;
-
- if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
- q->has_second_chip = true;
-
- mutex_init(&q->lock);
-
- /* iterate the subnodes. */
- for_each_available_child_of_node(dev->of_node, np) {
- /* skip the holes */
- if (!q->has_second_chip)
- i *= 2;
-
- nor = &q->nor[i];
- mtd = &nor->mtd;
-
- nor->dev = dev;
- spi_nor_set_flash_node(nor, np);
- nor->priv = q;
-
- if (q->nor_num > 1 && !mtd->name) {
- int spiflash_idx;
-
- ret = of_property_read_u32(np, "reg", &spiflash_idx);
- if (!ret) {
- mtd->name = devm_kasprintf(dev, GFP_KERNEL,
- "%s-%d",
- dev_name(dev),
- spiflash_idx);
- if (!mtd->name) {
- ret = -ENOMEM;
- goto mutex_failed;
- }
- } else {
- dev_warn(dev, "reg property is missing\n");
- }
- }
-
- /* fill the hooks */
- nor->read_reg = fsl_qspi_read_reg;
- nor->write_reg = fsl_qspi_write_reg;
- nor->read = fsl_qspi_read;
- nor->write = fsl_qspi_write;
- nor->erase = fsl_qspi_erase;
-
- nor->prepare = fsl_qspi_prep;
- nor->unprepare = fsl_qspi_unprep;
-
- ret = of_property_read_u32(np, "spi-max-frequency",
- &q->clk_rate);
- if (ret < 0)
- goto mutex_failed;
-
- /* set the chip address for READID */
- fsl_qspi_set_base_addr(q, nor);
-
- ret = spi_nor_scan(nor, NULL, &hwcaps);
- if (ret)
- goto mutex_failed;
-
- ret = mtd_device_register(mtd, NULL, 0);
- if (ret)
- goto mutex_failed;
-
- /* Set the correct NOR size now. */
- if (q->nor_size == 0) {
- q->nor_size = mtd->size;
-
- /* Map the SPI NOR to accessiable address */
- fsl_qspi_set_map_addr(q);
- }
-
- /*
- * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
- * may writes 265 bytes per time. The write is working in the
- * unit of the TX FIFO, not in the unit of the SPI NOR's page
- * size.
- *
- * So shrink the spi_nor->page_size if it is larger then the
- * TX FIFO.
- */
- if (nor->page_size > q->devtype_data->txfifo)
- nor->page_size = q->devtype_data->txfifo;
-
- i++;
- }
-
- /* finish the rest init. */
- ret = fsl_qspi_nor_setup_last(q);
- if (ret)
- goto last_init_failed;
-
- fsl_qspi_clk_disable_unprep(q);
- return 0;
-
-last_init_failed:
- for (i = 0; i < q->nor_num; i++) {
- /* skip the holes */
- if (!q->has_second_chip)
- i *= 2;
- mtd_device_unregister(&q->nor[i].mtd);
- }
-mutex_failed:
- mutex_destroy(&q->lock);
-irq_failed:
- fsl_qspi_clk_disable_unprep(q);
-clk_failed:
- dev_err(dev, "Freescale QuadSPI probe failed\n");
- return ret;
-}
-
-static int fsl_qspi_remove(struct platform_device *pdev)
-{
- struct fsl_qspi *q = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < q->nor_num; i++) {
- /* skip the holes */
- if (!q->has_second_chip)
- i *= 2;
- mtd_device_unregister(&q->nor[i].mtd);
- }
-
- /* disable the hardware */
- qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
- qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
-
- mutex_destroy(&q->lock);
-
- if (q->ahb_addr)
- iounmap(q->ahb_addr);
-
- return 0;
-}
-
-static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
-{
- return 0;
-}
-
-static int fsl_qspi_resume(struct platform_device *pdev)
-{
- int ret;
- struct fsl_qspi *q = platform_get_drvdata(pdev);
-
- ret = fsl_qspi_clk_prep_enable(q);
- if (ret)
- return ret;
-
- fsl_qspi_nor_setup(q);
- fsl_qspi_set_map_addr(q);
- fsl_qspi_nor_setup_last(q);
-
- fsl_qspi_clk_disable_unprep(q);
-
- return 0;
-}
-
-static struct platform_driver fsl_qspi_driver = {
- .driver = {
- .name = "fsl-quadspi",
- .of_match_table = fsl_qspi_dt_ids,
- },
- .probe = fsl_qspi_probe,
- .remove = fsl_qspi_remove,
- .suspend = fsl_qspi_suspend,
- .resume = fsl_qspi_resume,
-};
-module_platform_driver(fsl_qspi_driver);
-
-MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
-MODULE_AUTHOR("Freescale Semiconductor Inc.");
-MODULE_LICENSE("GPL v2");
--
2.7.4
Frieder Schrempf
2018-05-30 13:14:33 UTC
Permalink
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver and adjust the content to reflect the
new drivers settings.

Signed-off-by: Frieder Schrempf <***@exceet.de>
---
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65 ------------------
.../devicetree/bindings/spi/spi-fsl-qspi.txt | 69 ++++++++++++++++++++
2 files changed, 69 insertions(+), 65 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
deleted file mode 100644
index 483e9cf..0000000
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-* Freescale Quad Serial Peripheral Interface(QuadSPI)
-
-Required properties:
- - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
- "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
- "fsl,ls1021a-qspi"
- or
- "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
- "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
- - reg : the first contains the register location and length,
- the second contains the memory mapping address and length
- - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
- - interrupts : Should contain the interrupt for the device
- - clocks : The clocks needed by the QuadSPI controller
- - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
-
-Optional properties:
- - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
- Each bus can be connected with two NOR flashes.
- Most of the time, each bus only has one NOR flash
- connected, this is the default case.
- But if there are two NOR flashes connected to the
- bus, you should enable this property.
- (Please check the board's schematic.)
- - big-endian : That means the IP register is big endian
-
-Example:
-
-qspi0: ***@40044000 {
- compatible = "fsl,vf610-qspi";
- reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks VF610_CLK_QSPI0_EN>,
- <&clks VF610_CLK_QSPI0>;
- clock-names = "qspi_en", "qspi";
-
- flash0: ***@0 {
- ....
- };
-};
-
-Example showing the usage of two SPI NOR devices:
-
-&qspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi2>;
- status = "okay";
-
- flash0: ***@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- reg = <0>;
- };
-
- flash1: ***@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- reg = <1>;
- };
-};
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
new file mode 100644
index 0000000..0ee9cd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
@@ -0,0 +1,69 @@
+* Freescale Quad Serial Peripheral Interface(QuadSPI)
+
+Required properties:
+ - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
+ "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
+ "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
+ or
+ "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
+ - interrupts : Should contain the interrupt for the device
+ - clocks : The clocks needed by the QuadSPI controller
+ - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
+
+Optional properties:
+ - big-endian : That means the IP registers format is big endian
+
+Required SPI slave node properties:
+ - reg: There are two buses (A and B) with two chip selects each.
+ This encodes to which bus and CS the flash is connected:
+ <0>: Bus A, CS 0
+ <1>: Bus A, CS 1
+ <2>: Bus B, CS 0
+ <3>: Bus B, CS 1
+
+Example:
+
+qspi0: ***@40044000 {
+ compatible = "fsl,vf610-qspi";
+ reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_QSPI0_EN>,
+ <&clks VF610_CLK_QSPI0>;
+ clock-names = "qspi_en", "qspi";
+
+ flash0: ***@0 {
+ ....
+ };
+};
+
+Example showing the usage of two SPI NOR devices on bus A:
+
+&qspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi2>;
+ status = "okay";
+
+ flash0: ***@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <0>;
+ };
+
+ flash1: ***@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <1>;
+ };
+};
--
2.7.4
Frieder Schrempf
2018-05-30 15:14:32 UTC
Permalink
Hi Boris,
On Wed, 30 May 2018 15:14:33 +0200
Post by Frieder Schrempf
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver and adjust the content to reflect the
new drivers settings.
Maybe it's better to do that in 2 steps so that people can easily
identify what has changed in the bindings.
Ok, I can split this.

Thanks,

Frieder
Post by Frieder Schrempf
---
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65 ------------------
.../devicetree/bindings/spi/spi-fsl-qspi.txt | 69 ++++++++++++++++++++
2 files changed, 69 insertions(+), 65 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
deleted file mode 100644
index 483e9cf..0000000
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-* Freescale Quad Serial Peripheral Interface(QuadSPI)
-
- - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
- "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
- "fsl,ls1021a-qspi"
- or
- "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
- "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
- - reg : the first contains the register location and length,
- the second contains the memory mapping address and length
- - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
- - interrupts : Should contain the interrupt for the device
- - clocks : The clocks needed by the QuadSPI controller
- - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
-
- - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
- Each bus can be connected with two NOR flashes.
- Most of the time, each bus only has one NOR flash
- connected, this is the default case.
- But if there are two NOR flashes connected to the
- bus, you should enable this property.
- (Please check the board's schematic.)
- - big-endian : That means the IP register is big endian
-
-
- compatible = "fsl,vf610-qspi";
- reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks VF610_CLK_QSPI0_EN>,
- <&clks VF610_CLK_QSPI0>;
- clock-names = "qspi_en", "qspi";
-
- ....
- };
-};
-
-
-&qspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi2>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- reg = <0>;
- };
-
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- reg = <1>;
- };
-};
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
new file mode 100644
index 0000000..0ee9cd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
@@ -0,0 +1,69 @@
+* Freescale Quad Serial Peripheral Interface(QuadSPI)
+
+ - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
+ "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
+ "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
+ or
+ "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
+ - interrupts : Should contain the interrupt for the device
+ - clocks : The clocks needed by the QuadSPI controller
+ - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
+
+ - big-endian : That means the IP registers format is big endian
+
+ - reg: There are two buses (A and B) with two chip selects each.
+ <0>: Bus A, CS 0
+ <1>: Bus A, CS 1
+ <2>: Bus B, CS 0
+ <3>: Bus B, CS 1
+
+
+ compatible = "fsl,vf610-qspi";
+ reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_QSPI0_EN>,
+ <&clks VF610_CLK_QSPI0>;
+ clock-names = "qspi_en", "qspi";
+
+ ....
+ };
+};
+
+
+&qspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi2>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <0>;
+ };
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <1>;
+ };
+};
Continue reading on narkive:
Search results for '[PATCH 00/11] Port the FSL QSPI driver to the SPI framework' (newsgroups and mailing lists)
80
replies
[PATCH v3 0/8] Add the Quadspi driver for vf610-twr
started 2013-08-30 07:07:21 UTC
devicetree@vger.kernel.org
26
replies
[PATCH v5 0/9] Port the FSL QSPI driver to the SPI framework
started 2018-11-13 19:47:05 UTC
linux-mtd@lists.infradead.org
28
replies
[PATCH v4 00/10] Port the FSL QSPI driver to the SPI framework
started 2018-11-07 20:43:17 UTC
linux-mtd@lists.infradead.org
52
replies
[PATCH v2 01/12] spi: spi-mem: Extend the SPI mem interface to set a custom memory name
started 2018-07-05 16:14:57 UTC
linux-mtd@lists.infradead.org
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